[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
Re: [Qemu-devel] [PATCH v2 10/23] target-arm: implement CPACR register l
|
From: |
Sergey Fedorov |
|
Subject: |
Re: [Qemu-devel] [PATCH v2 10/23] target-arm: implement CPACR register logic |
|
Date: |
Thu, 15 May 2014 19:06:50 +0400 |
|
User-agent: |
Mozilla/5.0 (X11; Linux x86_64; rv:24.0) Gecko/20100101 Thunderbird/24.5.0 |
On 15.05.2014 18:44, Fabian Aggeler wrote:
>>> Please, look at disas_vfp_insn() and disas_neon_*_insn() functions.
>>> Looks like them should be updated. In that case do not forget to adjust
>>> arm_cpu_reset() so user emulation would be able to execute VFP/NEON
>>> instructions.
>>
>> See ARM ARM v7-AR B1.11.1
>>
>
> I don't quite get what you mean. Bits 20-24 of c1_coproc already get
> set to 1 for user emulation in arm_cpu_reset(). And disas_cfp_insn and
> disas_neon_*_insn() all check s->cpacr_fpen in the beginning (which
> gets set in cpu_get_tb_cpu_state() if bits 20-22 of c1_coproc are set
> to 3 or (1 && cpu is in user mode)).
>
> So I guess we should add some checks for NSACR, to only set that flag
> if the corresponding NSACR bit is set.
Sorry, you are right.
Regards,
Sergey.
[Qemu-devel] [PATCH v2 03/23] target-arm: adjust TTBCR for Security Extension feature, Fabian Aggeler, 2014/05/13
[Qemu-devel] [PATCH v2 12/23] target-arm: add SDER definition, Fabian Aggeler, 2014/05/13
[Qemu-devel] [PATCH v2 07/23] target-arm: reject switching to monitor mode from non-secure state, Fabian Aggeler, 2014/05/13
[Qemu-devel] [PATCH v2 08/23] target-arm: adjust arm_current_pl() for Security Extensions, Fabian Aggeler, 2014/05/13
[Qemu-devel] [PATCH v2 05/23] target-arm: add CPU Monitor mode, Fabian Aggeler, 2014/05/13
[Qemu-devel] [PATCH v2 04/23] target-arm: preserve RAO/WI bits of ARMv7 SCTLR, Fabian Aggeler, 2014/05/13