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Re: [Qemu-devel] [PATCH v2 01/23] target-arm: add new CPU feature for Se
From: |
Peter Maydell |
Subject: |
Re: [Qemu-devel] [PATCH v2 01/23] target-arm: add new CPU feature for Security Extensions |
Date: |
Wed, 21 May 2014 17:41:58 +0100 |
On 21 May 2014 17:33, Sergey Fedorov <address@hidden> wrote:
> On 21.05.2014 20:14, Christopher Covington wrote:
>> On 05/21/2014 10:46 AM, Peter Maydell wrote:
>>> (Also I'm not sure what the semantics of -kernel should be for
>>> TZ-supporting CPUs -- boot the kernel in S or NS ?)
>> While Linux works in secure mode, non-secure hypervisor mode is required for
>> KVM to work in the guest.
>>
>> "[Entry] in HYP mode ... is the recommended boot method ...."
>>
>> http://git.kernel.org/cgit/linux/kernel/git/torvalds/linux.git/tree/Documentation/arm/Booting#n183
Sure, but we don't implement HYP yet :-)
> AFAIK, in real hardware this switch to non-secure state is actually done
> by bootloader. Why don't implement this in Qemu bootloader stub so far?
If we want to have -kernel boot in NS then yes, the bootloader
stub is the place that code should go.
The difficulty with -kernel being NS is that some guest kernels
for some boards may be assuming that they will run in secure state
and can directly access h/w or registers which aren't accessible
from NS. I guess we need to implement it and then see if any of our
guest images stop working...
thanks
-- PMM
Re: [Qemu-devel] [PATCH v2 01/23] target-arm: add new CPU feature for Security Extensions, Peter Maydell, 2014/05/21
[Qemu-devel] [PATCH v2 02/23] target-arm: move SCR into Security Extensions register list, Fabian Aggeler, 2014/05/13
[Qemu-devel] [PATCH v2 09/23] target-arm: add non-secure Translation Block flag, Fabian Aggeler, 2014/05/13
[Qemu-devel] [PATCH v2 10/23] target-arm: implement CPACR register logic, Fabian Aggeler, 2014/05/13