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[Qemu-devel] [PATCH v5 06/23] target-arm: Make elr_el1 an array
From: |
Edgar E. Iglesias |
Subject: |
[Qemu-devel] [PATCH v5 06/23] target-arm: Make elr_el1 an array |
Date: |
Sun, 25 May 2014 11:08:35 +1000 |
From: "Edgar E. Iglesias" <address@hidden>
No functional change.
Prepares for future additions of the EL2 and 3 versions of this reg.
Reviewed-by: Peter Crosthwaite <address@hidden>
Signed-off-by: Edgar E. Iglesias <address@hidden>
---
target-arm/cpu.h | 2 +-
target-arm/helper-a64.c | 4 ++--
target-arm/helper.c | 3 ++-
target-arm/kvm64.c | 4 ++--
target-arm/machine.c | 2 +-
target-arm/op_helper.c | 6 +++---
6 files changed, 11 insertions(+), 10 deletions(-)
diff --git a/target-arm/cpu.h b/target-arm/cpu.h
index 5aa978d..fabfe9e 100644
--- a/target-arm/cpu.h
+++ b/target-arm/cpu.h
@@ -162,7 +162,7 @@ typedef struct CPUARMState {
uint32_t condexec_bits; /* IT bits. cpsr[15:10,26:25]. */
uint64_t daif; /* exception masks, in the bits they are in in PSTATE */
- uint64_t elr_el1; /* AArch64 ELR_EL1 */
+ uint64_t elr_el[2]; /* AArch64 exception link regs */
uint64_t sp_el[2]; /* AArch64 banked stack pointers */
/* System control coprocessor (cp15) */
diff --git a/target-arm/helper-a64.c b/target-arm/helper-a64.c
index bf921cc..7e5073b 100644
--- a/target-arm/helper-a64.c
+++ b/target-arm/helper-a64.c
@@ -491,13 +491,13 @@ void aarch64_cpu_do_interrupt(CPUState *cs)
env->banked_spsr[0] = pstate_read(env);
env->sp_el[arm_current_pl(env)] = env->xregs[31];
env->xregs[31] = env->sp_el[1];
- env->elr_el1 = env->pc;
+ env->elr_el[1] = env->pc;
} else {
env->banked_spsr[0] = cpsr_read(env);
if (!env->thumb) {
env->cp15.esr_el1 |= 1 << 25;
}
- env->elr_el1 = env->regs[15];
+ env->elr_el[1] = env->regs[15];
for (i = 0; i < 15; i++) {
env->xregs[i] = env->regs[i];
diff --git a/target-arm/helper.c b/target-arm/helper.c
index 417161e..6d6601e 100644
--- a/target-arm/helper.c
+++ b/target-arm/helper.c
@@ -2055,7 +2055,8 @@ static const ARMCPRegInfo v8_cp_reginfo[] = {
{ .name = "ELR_EL1", .state = ARM_CP_STATE_AA64,
.type = ARM_CP_NO_MIGRATE,
.opc0 = 3, .opc1 = 0, .crn = 4, .crm = 0, .opc2 = 1,
- .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, elr_el1) },
+ .access = PL1_RW,
+ .fieldoffset = offsetof(CPUARMState, elr_el[1]) },
{ .name = "SPSR_EL1", .state = ARM_CP_STATE_AA64,
.type = ARM_CP_NO_MIGRATE,
.opc0 = 3, .opc1 = 0, .crn = 4, .crm = 0, .opc2 = 0,
diff --git a/target-arm/kvm64.c b/target-arm/kvm64.c
index c729b9e..70f311b 100644
--- a/target-arm/kvm64.c
+++ b/target-arm/kvm64.c
@@ -161,7 +161,7 @@ int kvm_arch_put_registers(CPUState *cs, int level)
}
reg.id = AARCH64_CORE_REG(elr_el1);
- reg.addr = (uintptr_t) &env->elr_el1;
+ reg.addr = (uintptr_t) &env->elr_el[1];
ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, ®);
if (ret) {
return ret;
@@ -241,7 +241,7 @@ int kvm_arch_get_registers(CPUState *cs)
}
reg.id = AARCH64_CORE_REG(elr_el1);
- reg.addr = (uintptr_t) &env->elr_el1;
+ reg.addr = (uintptr_t) &env->elr_el[1];
ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, ®);
if (ret) {
return ret;
diff --git a/target-arm/machine.c b/target-arm/machine.c
index 5092dcd..b0fa46d 100644
--- a/target-arm/machine.c
+++ b/target-arm/machine.c
@@ -238,7 +238,7 @@ const VMStateDescription vmstate_arm_cpu = {
VMSTATE_UINT32_ARRAY(env.banked_r14, ARMCPU, 6),
VMSTATE_UINT32_ARRAY(env.usr_regs, ARMCPU, 5),
VMSTATE_UINT32_ARRAY(env.fiq_regs, ARMCPU, 5),
- VMSTATE_UINT64(env.elr_el1, ARMCPU),
+ VMSTATE_UINT64(env.elr_el[1], ARMCPU),
VMSTATE_UINT64_ARRAY(env.sp_el, ARMCPU, 2),
/* The length-check must come before the arrays to avoid
* incoming data possibly overflowing the array.
diff --git a/target-arm/op_helper.c b/target-arm/op_helper.c
index fb90676..f120b02 100644
--- a/target-arm/op_helper.c
+++ b/target-arm/op_helper.c
@@ -406,7 +406,7 @@ void HELPER(exception_return)(CPUARMState *env)
env->regs[i] = env->xregs[i];
}
- env->regs[15] = env->elr_el1 & ~0x1;
+ env->regs[15] = env->elr_el[1] & ~0x1;
} else {
new_el = extract32(spsr, 2, 2);
if (new_el > 1) {
@@ -424,7 +424,7 @@ void HELPER(exception_return)(CPUARMState *env)
env->aarch64 = 1;
pstate_write(env, spsr);
env->xregs[31] = env->sp_el[new_el];
- env->pc = env->elr_el1;
+ env->pc = env->elr_el[1];
}
return;
@@ -438,7 +438,7 @@ illegal_return:
* no change to exception level, execution state or stack pointer
*/
env->pstate |= PSTATE_IL;
- env->pc = env->elr_el1;
+ env->pc = env->elr_el[1];
spsr &= PSTATE_NZCV | PSTATE_DAIF;
spsr |= pstate_read(env) & ~(PSTATE_NZCV | PSTATE_DAIF);
pstate_write(env, spsr);
--
1.8.3.2
- [Qemu-devel] [PATCH v5 00/23] target-arm: Preparations for A64 EL2 and 3, Edgar E. Iglesias, 2014/05/24
- [Qemu-devel] [PATCH v5 01/23] target-arm: Move get_mem_index to translate.h, Edgar E. Iglesias, 2014/05/24
- [Qemu-devel] [PATCH v5 02/23] target-arm/translate.c: Clean up mmu index handling for ldrt/strt, Edgar E. Iglesias, 2014/05/24
- [Qemu-devel] [PATCH v5 03/23] target-arm/translate.c: Use get_mem_index() for SRS memory accesses, Edgar E. Iglesias, 2014/05/24
- [Qemu-devel] [PATCH v5 04/23] target-arm: A32: Use get_mem_index for load/stores, Edgar E. Iglesias, 2014/05/24
- [Qemu-devel] [PATCH v5 05/23] target-arm: Use a 1:1 mapping between EL and MMU index, Edgar E. Iglesias, 2014/05/24
- [Qemu-devel] [PATCH v5 06/23] target-arm: Make elr_el1 an array,
Edgar E. Iglesias <=
- [Qemu-devel] [PATCH v5 07/23] target-arm: Make esr_el1 an array, Edgar E. Iglesias, 2014/05/24
- [Qemu-devel] [PATCH v5 08/23] target-arm: c12_vbar -> vbar_el[], Edgar E. Iglesias, 2014/05/24
- [Qemu-devel] [PATCH v5 09/23] target-arm: A64: Add SP entries for EL2 and 3, Edgar E. Iglesias, 2014/05/24
- [Qemu-devel] [PATCH v5 10/23] target-arm: A64: Add ELR entries for EL2 and 3, Edgar E. Iglesias, 2014/05/24
- [Qemu-devel] [PATCH v5 11/23] target-arm: Add SPSR entries for EL2/HYP and EL3/MON, Edgar E. Iglesias, 2014/05/24
- [Qemu-devel] [PATCH v5 12/23] target-arm: A64: Introduce aarch64_banked_spsr_index(), Edgar E. Iglesias, 2014/05/24
- [Qemu-devel] [PATCH v5 13/23] target-arm: Add a feature flag for EL2, Edgar E. Iglesias, 2014/05/24
- [Qemu-devel] [PATCH v5 14/23] target-arm: Add a feature flag for EL3, Edgar E. Iglesias, 2014/05/24
- [Qemu-devel] [PATCH v5 15/23] target-arm: Register EL2 versions of ELR and SPSR, Edgar E. Iglesias, 2014/05/24
- [Qemu-devel] [PATCH v5 16/23] target-arm: Register EL3 versions of ELR and SPSR, Edgar E. Iglesias, 2014/05/24