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[Qemu-devel] [PATCH v5 08/23] target-arm: c12_vbar -> vbar_el[]
From: |
Edgar E. Iglesias |
Subject: |
[Qemu-devel] [PATCH v5 08/23] target-arm: c12_vbar -> vbar_el[] |
Date: |
Sun, 25 May 2014 11:08:37 +1000 |
From: "Edgar E. Iglesias" <address@hidden>
No functional change.
Preparation for adding EL2 and 3 versions of this reg.
Reviewed-by: Peter Crosthwaite <address@hidden>
Signed-off-by: Edgar E. Iglesias <address@hidden>
---
target-arm/cpu.h | 2 +-
target-arm/helper-a64.c | 2 +-
target-arm/helper.c | 6 +++---
3 files changed, 5 insertions(+), 5 deletions(-)
diff --git a/target-arm/cpu.h b/target-arm/cpu.h
index a3cf375..62d85ff 100644
--- a/target-arm/cpu.h
+++ b/target-arm/cpu.h
@@ -198,7 +198,7 @@ typedef struct CPUARMState {
uint32_t c9_pmuserenr; /* perf monitor user enable */
uint32_t c9_pminten; /* perf monitor interrupt enables */
uint64_t mair_el1;
- uint64_t c12_vbar; /* vector base address register */
+ uint64_t vbar_el[2]; /* vector base address register */
uint32_t c13_fcse; /* FCSE PID. */
uint64_t contextidr_el1; /* Context ID. */
uint64_t tpidr_el0; /* User RW Thread register. */
diff --git a/target-arm/helper-a64.c b/target-arm/helper-a64.c
index 13c5865..b8e6d56 100644
--- a/target-arm/helper-a64.c
+++ b/target-arm/helper-a64.c
@@ -443,7 +443,7 @@ void aarch64_cpu_do_interrupt(CPUState *cs)
{
ARMCPU *cpu = ARM_CPU(cs);
CPUARMState *env = &cpu->env;
- target_ulong addr = env->cp15.c12_vbar;
+ target_ulong addr = env->cp15.vbar_el[1];
int i;
if (arm_current_pl(env) == 0) {
diff --git a/target-arm/helper.c b/target-arm/helper.c
index 107cd5f..bba7297 100644
--- a/target-arm/helper.c
+++ b/target-arm/helper.c
@@ -657,7 +657,7 @@ static void vbar_write(CPUARMState *env, const ARMCPRegInfo
*ri,
* contexts. (ARMv8 would permit us to do no masking at all, but ARMv7
* requires the bottom five bits to be RAZ/WI because they're UNK/SBZP.)
*/
- env->cp15.c12_vbar = value & ~0x1FULL;
+ env->cp15.vbar_el[1] = value & ~0x1FULL;
}
static uint64_t ccsidr_read(CPUARMState *env, const ARMCPRegInfo *ri)
@@ -766,7 +766,7 @@ static const ARMCPRegInfo v7_cp_reginfo[] = {
{ .name = "VBAR", .state = ARM_CP_STATE_BOTH,
.opc0 = 3, .crn = 12, .crm = 0, .opc1 = 0, .opc2 = 0,
.access = PL1_RW, .writefn = vbar_write,
- .fieldoffset = offsetof(CPUARMState, cp15.c12_vbar),
+ .fieldoffset = offsetof(CPUARMState, cp15.vbar_el[1]),
.resetvalue = 0 },
{ .name = "SCR", .cp = 15, .crn = 1, .crm = 1, .opc1 = 0, .opc2 = 0,
.access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c1_scr),
@@ -3379,7 +3379,7 @@ void arm_cpu_do_interrupt(CPUState *cs)
* and is never in monitor mode this feature is always active.
* Note: only bits 31:5 are valid.
*/
- addr += env->cp15.c12_vbar;
+ addr += env->cp15.vbar_el[1];
}
switch_mode (env, new_mode);
env->spsr = cpsr_read(env);
--
1.8.3.2
- [Qemu-devel] [PATCH v5 00/23] target-arm: Preparations for A64 EL2 and 3, Edgar E. Iglesias, 2014/05/24
- [Qemu-devel] [PATCH v5 01/23] target-arm: Move get_mem_index to translate.h, Edgar E. Iglesias, 2014/05/24
- [Qemu-devel] [PATCH v5 02/23] target-arm/translate.c: Clean up mmu index handling for ldrt/strt, Edgar E. Iglesias, 2014/05/24
- [Qemu-devel] [PATCH v5 03/23] target-arm/translate.c: Use get_mem_index() for SRS memory accesses, Edgar E. Iglesias, 2014/05/24
- [Qemu-devel] [PATCH v5 04/23] target-arm: A32: Use get_mem_index for load/stores, Edgar E. Iglesias, 2014/05/24
- [Qemu-devel] [PATCH v5 05/23] target-arm: Use a 1:1 mapping between EL and MMU index, Edgar E. Iglesias, 2014/05/24
- [Qemu-devel] [PATCH v5 06/23] target-arm: Make elr_el1 an array, Edgar E. Iglesias, 2014/05/24
- [Qemu-devel] [PATCH v5 07/23] target-arm: Make esr_el1 an array, Edgar E. Iglesias, 2014/05/24
- [Qemu-devel] [PATCH v5 08/23] target-arm: c12_vbar -> vbar_el[],
Edgar E. Iglesias <=
- [Qemu-devel] [PATCH v5 09/23] target-arm: A64: Add SP entries for EL2 and 3, Edgar E. Iglesias, 2014/05/24
- [Qemu-devel] [PATCH v5 10/23] target-arm: A64: Add ELR entries for EL2 and 3, Edgar E. Iglesias, 2014/05/24
- [Qemu-devel] [PATCH v5 11/23] target-arm: Add SPSR entries for EL2/HYP and EL3/MON, Edgar E. Iglesias, 2014/05/24
- [Qemu-devel] [PATCH v5 12/23] target-arm: A64: Introduce aarch64_banked_spsr_index(), Edgar E. Iglesias, 2014/05/24
- [Qemu-devel] [PATCH v5 13/23] target-arm: Add a feature flag for EL2, Edgar E. Iglesias, 2014/05/24
- [Qemu-devel] [PATCH v5 14/23] target-arm: Add a feature flag for EL3, Edgar E. Iglesias, 2014/05/24
- [Qemu-devel] [PATCH v5 15/23] target-arm: Register EL2 versions of ELR and SPSR, Edgar E. Iglesias, 2014/05/24
- [Qemu-devel] [PATCH v5 16/23] target-arm: Register EL3 versions of ELR and SPSR, Edgar E. Iglesias, 2014/05/24
- [Qemu-devel] [PATCH v5 17/23] target-arm: A64: Forbid ERET to higher or unimplemented ELs, Edgar E. Iglesias, 2014/05/24
- [Qemu-devel] [PATCH v5 18/23] target-arm: A64: Trap ERET from EL0 at translation time, Edgar E. Iglesias, 2014/05/24