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[Qemu-devel] [PULL 03/26] target-arm: implement CPACR register logic for
From: |
Peter Maydell |
Subject: |
[Qemu-devel] [PULL 03/26] target-arm: implement CPACR register logic for ARMv7 |
Date: |
Tue, 27 May 2014 17:28:11 +0100 |
From: Fabian Aggeler <address@hidden>
In ARMv7 the CPACR register allows to control access rights to
coprocessor 0-13 interfaces. Bits corresponding to unimplemented
coprocessors should be RAZ/WI. Bits ASEDIS, D32DIS, TRCDIS are
UNK/SBZP if VFP is not implemented and RAO/WI in some cases.
Treating TRCDIS as RAZ/WI since we neither implement a trace
macrocell nor a CP14 interface to the trace macrocell registers.
Since CPACR bits for VFP/Neon access are honoured with the CPACR_FPEN
bit in the TB flags, flushing the TLB is not necessary anymore.
Signed-off-by: Fabian Aggeler <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>
---
target-arm/helper.c | 32 ++++++++++++++++++++++++++++----
1 file changed, 28 insertions(+), 4 deletions(-)
diff --git a/target-arm/helper.c b/target-arm/helper.c
index 417161e..cb59f00 100644
--- a/target-arm/helper.c
+++ b/target-arm/helper.c
@@ -477,11 +477,35 @@ static const ARMCPRegInfo not_v7_cp_reginfo[] = {
static void cpacr_write(CPUARMState *env, const ARMCPRegInfo *ri,
uint64_t value)
{
- if (env->cp15.c1_coproc != value) {
- env->cp15.c1_coproc = value;
- /* ??? Is this safe when called from within a TB? */
- tb_flush(env);
+ uint32_t mask = 0;
+
+ /* In ARMv8 most bits of CPACR_EL1 are RES0. */
+ if (!arm_feature(env, ARM_FEATURE_V8)) {
+ /* ARMv7 defines bits for unimplemented coprocessors as RAZ/WI.
+ * ASEDIS [31] and D32DIS [30] are both UNK/SBZP without VFP.
+ * TRCDIS [28] is RAZ/WI since we do not implement a trace macrocell.
+ */
+ if (arm_feature(env, ARM_FEATURE_VFP)) {
+ /* VFP coprocessor: cp10 & cp11 [23:20] */
+ mask |= (1 << 31) | (1 << 30) | (0xf << 20);
+
+ if (!arm_feature(env, ARM_FEATURE_NEON)) {
+ /* ASEDIS [31] bit is RAO/WI */
+ value |= (1 << 31);
+ }
+
+ /* VFPv3 and upwards with NEON implement 32 double precision
+ * registers (D0-D31).
+ */
+ if (!arm_feature(env, ARM_FEATURE_NEON) ||
+ !arm_feature(env, ARM_FEATURE_VFP3)) {
+ /* D32DIS [30] is RAO/WI if D16-31 are not implemented. */
+ value |= (1 << 30);
+ }
+ }
+ value &= mask;
}
+ env->cp15.c1_coproc = value;
}
static const ARMCPRegInfo v6_cp_reginfo[] = {
--
1.9.2
- [Qemu-devel] [PULL 25/26] target-arm: A64: Register VBAR_EL2, (continued)
- [Qemu-devel] [PULL 25/26] target-arm: A64: Register VBAR_EL2, Peter Maydell, 2014/05/27
- [Qemu-devel] [PULL 14/26] target-arm: Add SPSR entries for EL2/HYP and EL3/MON, Peter Maydell, 2014/05/27
- [Qemu-devel] [PULL 08/26] target-arm: Use a 1:1 mapping between EL and MMU index, Peter Maydell, 2014/05/27
- [Qemu-devel] [PULL 13/26] target-arm: A64: Add ELR entries for EL2 and 3, Peter Maydell, 2014/05/27
- [Qemu-devel] [PULL 20/26] target-arm: A64: Forbid ERET to higher or unimplemented ELs, Peter Maydell, 2014/05/27
- [Qemu-devel] [PULL 05/26] target-arm/translate.c: Clean up mmu index handling for ldrt/strt, Peter Maydell, 2014/05/27
- [Qemu-devel] [PULL 06/26] target-arm/translate.c: Use get_mem_index() for SRS memory accesses, Peter Maydell, 2014/05/27
- [Qemu-devel] [PULL 02/26] hw/display/pxa2xx_lcd: Fix 16bpp+alpha and 18bpp+alpha palette formats, Peter Maydell, 2014/05/27
- [Qemu-devel] [PULL 07/26] target-arm: A32: Use get_mem_index for load/stores, Peter Maydell, 2014/05/27
- [Qemu-devel] [PULL 09/26] target-arm: Make elr_el1 an array, Peter Maydell, 2014/05/27
- [Qemu-devel] [PULL 03/26] target-arm: implement CPACR register logic for ARMv7,
Peter Maydell <=
- [Qemu-devel] [PULL 04/26] target-arm: Move get_mem_index to translate.h, Peter Maydell, 2014/05/27
- Re: [Qemu-devel] [PULL 00/26] target-arm queue, Peter Maydell, 2014/05/28