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Re: [Qemu-devel] [PATCH 07/21] target-mips: signal RI Exception on DSP a
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From: |
Aurelien Jarno |
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Subject: |
Re: [Qemu-devel] [PATCH 07/21] target-mips: signal RI Exception on DSP and Loongson instructions |
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Date: |
Fri, 30 May 2014 22:09:11 +0200 |
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User-agent: |
Mutt/1.5.21 (2010-09-15) |
On Fri, May 30, 2014 at 03:47:45PM +0100, Leon Alrae wrote:
> Move DSP and Loongson instruction to *_legacy functions as they have been
> removed in R6.
>
> Signed-off-by: Leon Alrae <address@hidden>
> ---
> target-mips/translate.c | 195
> ++++++++++++++++++++++++-----------------------
> 1 files changed, 98 insertions(+), 97 deletions(-)
>
> diff --git a/target-mips/translate.c b/target-mips/translate.c
> index 9763542..8f1ade5 100644
> --- a/target-mips/translate.c
> +++ b/target-mips/translate.c
> @@ -14732,6 +14732,26 @@ static void decode_opc_special2_legacy(CPUMIPSState
> *env, DisasContext *ctx)
> case OPC_MUL:
> gen_arith(ctx, op1, rd, rs, rt);
> break;
> + case OPC_DIV_G_2F:
> + case OPC_DIVU_G_2F:
> + case OPC_MULT_G_2F:
> + case OPC_MULTU_G_2F:
> + case OPC_MOD_G_2F:
> + case OPC_MODU_G_2F:
> + check_insn(ctx, INSN_LOONGSON2F);
> + gen_loongson_integer(ctx, op1, rd, rs, rt);
> + break;
> +#if defined(TARGET_MIPS64)
> + case OPC_DMULT_G_2F:
> + case OPC_DMULTU_G_2F:
> + case OPC_DDIV_G_2F:
> + case OPC_DDIVU_G_2F:
> + case OPC_DMOD_G_2F:
> + case OPC_DMODU_G_2F:
> + check_insn(ctx, INSN_LOONGSON2F);
> + gen_loongson_integer(ctx, op1, rd, rs, rt);
> + break;
> +#endif
> default: /* Invalid */
> MIPS_INVAL("special2_legacy");
> generate_exception(ctx, EXCP_RI);
> @@ -14741,11 +14761,10 @@ static void decode_opc_special2_legacy(CPUMIPSState
> *env, DisasContext *ctx)
>
> static void decode_opc_special2(CPUMIPSState *env, DisasContext *ctx)
> {
> - int rs, rt, rd;
> + int rs, rd;
> uint32_t op1;
>
> rs = (ctx->opcode >> 21) & 0x1f;
> - rt = (ctx->opcode >> 16) & 0x1f;
> rd = (ctx->opcode >> 11) & 0x1f;
>
> op1 = MASK_SPECIAL2(ctx->opcode);
> @@ -14767,15 +14786,6 @@ static void decode_opc_special2(CPUMIPSState *env,
> DisasContext *ctx)
> }
> /* Treat as NOP. */
> break;
> - case OPC_DIV_G_2F:
> - case OPC_DIVU_G_2F:
> - case OPC_MULT_G_2F:
> - case OPC_MULTU_G_2F:
> - case OPC_MOD_G_2F:
> - case OPC_MODU_G_2F:
> - check_insn(ctx, INSN_LOONGSON2F);
> - gen_loongson_integer(ctx, op1, rd, rs, rt);
> - break;
> #if defined(TARGET_MIPS64)
> case OPC_DCLO:
> case OPC_DCLZ:
> @@ -14783,15 +14793,6 @@ static void decode_opc_special2(CPUMIPSState *env,
> DisasContext *ctx)
> check_mips_64(ctx);
> gen_cl(ctx, op1, rd, rs);
> break;
> - case OPC_DMULT_G_2F:
> - case OPC_DMULTU_G_2F:
> - case OPC_DDIV_G_2F:
> - case OPC_DDIVU_G_2F:
> - case OPC_DMOD_G_2F:
> - case OPC_DMODU_G_2F:
> - check_insn(ctx, INSN_LOONGSON2F);
> - gen_loongson_integer(ctx, op1, rd, rs, rt);
> - break;
> #endif
> default:
> if (ctx->insn_flags & ISA_MIPS32R6) {
> @@ -14829,80 +14830,15 @@ static void decode_opc_special3_r6(CPUMIPSState
> *env, DisasContext *ctx)
>
> static void decode_opc_special3_legacy(CPUMIPSState *env, DisasContext *ctx)
> {
> - uint32_t op1;
> -#if defined(TARGET_MIPS64)
> - int rd = (ctx->opcode >> 11) & 0x1f;
> - int rs = (ctx->opcode >> 21) & 0x1f;
> - int rt = (ctx->opcode >> 16) & 0x1f;
> -#endif
> -
> - op1 = MASK_SPECIAL3(ctx->opcode);
> - switch (op1) {
> -#if defined(TARGET_MIPS64)
> - case OPC_DDIV_G_2E ... OPC_DDIVU_G_2E:
> - case OPC_DMULT_G_2E ... OPC_DMULTU_G_2E:
> - case OPC_DMOD_G_2E ... OPC_DMODU_G_2E:
> - check_insn(ctx, INSN_LOONGSON2E);
> - gen_loongson_integer(ctx, op1, rd, rs, rt);
> - break;
> -#endif
> - default: /* Invalid */
> - MIPS_INVAL("special3_legacy");
> - generate_exception(ctx, EXCP_RI);
> - break;
> - }
> -}
> -
> -static void decode_opc_special3(CPUMIPSState *env, DisasContext *ctx)
> -{
> - int rs, rt, rd, sa;
> + int rs, rt, rd;
> uint32_t op1, op2;
>
> rs = (ctx->opcode >> 21) & 0x1f;
> rt = (ctx->opcode >> 16) & 0x1f;
> rd = (ctx->opcode >> 11) & 0x1f;
> - sa = (ctx->opcode >> 6) & 0x1f;
>
> op1 = MASK_SPECIAL3(ctx->opcode);
> switch (op1) {
> - case OPC_EXT:
> - case OPC_INS:
> - check_insn(ctx, ISA_MIPS32R2);
> - gen_bitops(ctx, op1, rt, rs, sa, rd);
> - break;
> - case OPC_BSHFL:
> - check_insn(ctx, ISA_MIPS32R2);
> - op2 = MASK_BSHFL(ctx->opcode);
> - gen_bshfl(ctx, op2, rt, rd);
> - break;
> - case OPC_RDHWR:
> - gen_rdhwr(ctx, rt, rd);
> - break;
> - case OPC_FORK:
> - check_insn(ctx, ASE_MT);
> - {
> - TCGv t0 = tcg_temp_new();
> - TCGv t1 = tcg_temp_new();
> -
> - gen_load_gpr(t0, rt);
> - gen_load_gpr(t1, rs);
> - gen_helper_fork(t0, t1);
> - tcg_temp_free(t0);
> - tcg_temp_free(t1);
> - }
> - break;
> - case OPC_YIELD:
> - check_insn(ctx, ASE_MT);
> - {
> - TCGv t0 = tcg_temp_new();
> -
> - save_cpu_state(ctx, 1);
> - gen_load_gpr(t0, rs);
> - gen_helper_yield(t0, cpu_env, t0);
> - gen_store_gpr(t0, rd);
> - tcg_temp_free(t0);
> - }
> - break;
> case OPC_DIV_G_2E ... OPC_DIVU_G_2E:
> case OPC_MOD_G_2E ... OPC_MODU_G_2E:
> case OPC_MULT_G_2E ... OPC_MULTU_G_2E:
> @@ -15170,17 +15106,11 @@ static void decode_opc_special3(CPUMIPSState *env,
> DisasContext *ctx)
> }
> break;
> #if defined(TARGET_MIPS64)
> - case OPC_DEXTM ... OPC_DEXT:
> - case OPC_DINSM ... OPC_DINS:
> - check_insn(ctx, ISA_MIPS64R2);
> - check_mips_64(ctx);
> - gen_bitops(ctx, op1, rt, rs, sa, rd);
> - break;
> - case OPC_DBSHFL:
> - check_insn(ctx, ISA_MIPS64R2);
> - check_mips_64(ctx);
> - op2 = MASK_DBSHFL(ctx->opcode);
> - gen_bshfl(ctx, op2, rt, rd);
> + case OPC_DDIV_G_2E ... OPC_DDIVU_G_2E:
> + case OPC_DMULT_G_2E ... OPC_DMULTU_G_2E:
> + case OPC_DMOD_G_2E ... OPC_DMODU_G_2E:
> + check_insn(ctx, INSN_LOONGSON2E);
> + gen_loongson_integer(ctx, op1, rd, rs, rt);
> break;
> case OPC_ABSQ_S_QH_DSP:
> op2 = MASK_ABSQ_S_QH(ctx->opcode);
> @@ -15411,6 +15341,77 @@ static void decode_opc_special3(CPUMIPSState *env,
> DisasContext *ctx)
> break;
> #endif
> default: /* Invalid */
> + MIPS_INVAL("special3_legacy");
> + generate_exception(ctx, EXCP_RI);
> + break;
> + }
> +}
> +
> +static void decode_opc_special3(CPUMIPSState *env, DisasContext *ctx)
> +{
> + int rs, rt, rd, sa;
> + uint32_t op1, op2;
> +
> + rs = (ctx->opcode >> 21) & 0x1f;
> + rt = (ctx->opcode >> 16) & 0x1f;
> + rd = (ctx->opcode >> 11) & 0x1f;
> + sa = (ctx->opcode >> 6) & 0x1f;
> +
> + op1 = MASK_SPECIAL3(ctx->opcode);
> + switch (op1) {
> + case OPC_EXT:
> + case OPC_INS:
> + check_insn(ctx, ISA_MIPS32R2);
> + gen_bitops(ctx, op1, rt, rs, sa, rd);
> + break;
> + case OPC_BSHFL:
> + check_insn(ctx, ISA_MIPS32R2);
> + op2 = MASK_BSHFL(ctx->opcode);
> + gen_bshfl(ctx, op2, rt, rd);
> + break;
> +#if defined(TARGET_MIPS64)
> + case OPC_DEXTM ... OPC_DEXT:
> + case OPC_DINSM ... OPC_DINS:
> + check_insn(ctx, ISA_MIPS64R2);
> + check_mips_64(ctx);
> + gen_bitops(ctx, op1, rt, rs, sa, rd);
> + break;
> + case OPC_DBSHFL:
> + check_insn(ctx, ISA_MIPS64R2);
> + check_mips_64(ctx);
> + op2 = MASK_DBSHFL(ctx->opcode);
> + gen_bshfl(ctx, op2, rt, rd);
> + break;
> +#endif
> + case OPC_RDHWR:
> + gen_rdhwr(ctx, rt, rd);
> + break;
> + case OPC_FORK:
> + check_insn(ctx, ASE_MT);
> + {
> + TCGv t0 = tcg_temp_new();
> + TCGv t1 = tcg_temp_new();
> +
> + gen_load_gpr(t0, rt);
> + gen_load_gpr(t1, rs);
> + gen_helper_fork(t0, t1);
> + tcg_temp_free(t0);
> + tcg_temp_free(t1);
> + }
> + break;
> + case OPC_YIELD:
> + check_insn(ctx, ASE_MT);
> + {
> + TCGv t0 = tcg_temp_new();
> +
> + save_cpu_state(ctx, 1);
> + gen_load_gpr(t0, rs);
> + gen_helper_yield(t0, cpu_env, t0);
> + gen_store_gpr(t0, rd);
> + tcg_temp_free(t0);
> + }
> + break;
> + default: /* Invalid */
> if (ctx->insn_flags & ISA_MIPS32R6) {
> decode_opc_special3_r6(env, ctx);
> } else {
Reviewed-by: Aurelien Jarno <address@hidden>
--
Aurelien Jarno GPG: 1024D/F1BCDB73
address@hidden http://www.aurel32.net
- [Qemu-devel] [PATCH 03/21] target-mips: add SELEQZ and SELNEZ instructions, (continued)
- [Qemu-devel] [PATCH 03/21] target-mips: add SELEQZ and SELNEZ instructions, Leon Alrae, 2014/05/30
- [Qemu-devel] [PATCH 05/21] target-mips: extract decode_opc_special* from decode_opc, Leon Alrae, 2014/05/30
- [Qemu-devel] [PATCH 08/21] target-mips: move PREF, CACHE, LLD and SCD instructions, Leon Alrae, 2014/05/30
- [Qemu-devel] [PATCH 06/21] target-mips: split decode_opc_special* into *_r6 and *_legacy, Leon Alrae, 2014/05/30
- [Qemu-devel] [PATCH 07/21] target-mips: signal RI Exception on DSP and Loongson instructions, Leon Alrae, 2014/05/30
- Re: [Qemu-devel] [PATCH 07/21] target-mips: signal RI Exception on DSP and Loongson instructions,
Aurelien Jarno <=
- [Qemu-devel] [PATCH 11/21] target-mips: Status.UX/SX/KX enable 32-bit address wrapping, Leon Alrae, 2014/05/30
- [Qemu-devel] [PATCH 10/21] target-mips: move CLO, DCLO, CLZ, DCLZ, SDBBP and free special2 in R6, Leon Alrae, 2014/05/30
- [Qemu-devel] [PATCH 09/21] target-mips: redefine Integer Multiply and Divide instructions, Leon Alrae, 2014/05/30
- [Qemu-devel] [PATCH 12/21] target-mips: add ALIGN, DALIGN, BITSWAP and DBITSWAP instructions, Leon Alrae, 2014/05/30