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[Qemu-devel] [PULL 19/20] target-arm: Fix errors in writes to generic ti
From: |
Peter Maydell |
Subject: |
[Qemu-devel] [PULL 19/20] target-arm: Fix errors in writes to generic timer control registers |
Date: |
Mon, 9 Jun 2014 15:57:37 +0100 |
The code for handling writes to the generic timer control registers
had several bugs:
* ISTATUS (bit 2) is read-only but we forced it to zero on any write
* the check for "was IMASK (bit 1) toggled?" incorrectly used '&' where
it should be '^'
* the handling of IMASK was inverted: we should set the IRQ if
ISTATUS is set and IMASK is clear, not if both are set
The combination of these bugs meant that when running a Linux guest
that uses the generic timers we would fairly quickly end up either
forgetting that the timer output should be asserted, or failing to
set the IRQ when the timer was unmasked. The result is that the guest
never gets any more timer interrupts.
Signed-off-by: Peter Maydell <address@hidden>
Message-id: address@hidden
Cc: address@hidden
---
target-arm/helper.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/target-arm/helper.c b/target-arm/helper.c
index 2b7a904..562545f 100644
--- a/target-arm/helper.c
+++ b/target-arm/helper.c
@@ -1040,16 +1040,16 @@ static void gt_ctl_write(CPUARMState *env, const
ARMCPRegInfo *ri,
int timeridx = ri->crm & 1;
uint32_t oldval = env->cp15.c14_timer[timeridx].ctl;
- env->cp15.c14_timer[timeridx].ctl = value & 3;
+ env->cp15.c14_timer[timeridx].ctl = deposit64(oldval, 0, 2, value);
if ((oldval ^ value) & 1) {
/* Enable toggled */
gt_recalc_timer(cpu, timeridx);
- } else if ((oldval & value) & 2) {
+ } else if ((oldval ^ value) & 2) {
/* IMASK toggled: don't need to recalculate,
* just set the interrupt line based on ISTATUS
*/
qemu_set_irq(cpu->gt_timer_outputs[timeridx],
- (oldval & 4) && (value & 2));
+ (oldval & 4) && !(value & 2));
}
}
--
1.9.2
- [Qemu-devel] [PULL 00/20] target-arm queue, Peter Maydell, 2014/06/09
- [Qemu-devel] [PULL 20/20] target-arm: Delete unused iwmmxt_msadb helper, Peter Maydell, 2014/06/09
- [Qemu-devel] [PULL 18/20] target-arm: A64: Implement two-register SHA instructions, Peter Maydell, 2014/06/09
- [Qemu-devel] [PULL 19/20] target-arm: Fix errors in writes to generic timer control registers,
Peter Maydell <=
- [Qemu-devel] [PULL 15/20] target-arm: A32/T32: Mask CRC value in calling code, not helper, Peter Maydell, 2014/06/09
- [Qemu-devel] [PULL 16/20] target-arm: A64: Implement AES instructions, Peter Maydell, 2014/06/09
- [Qemu-devel] [PULL 13/20] target-arm: VFPv4 implies half-precision extension, Peter Maydell, 2014/06/09
- [Qemu-devel] [PULL 14/20] target-arm: A64: Implement CRC instructions, Peter Maydell, 2014/06/09
- [Qemu-devel] [PULL 11/20] target-arm: Remove unnecessary setting of feature bits, Peter Maydell, 2014/06/09
- [Qemu-devel] [PULL 09/20] target-arm: A64: Use PMULL feature bit for PMULL, Peter Maydell, 2014/06/09
- [Qemu-devel] [PULL 10/20] target-arm: arm_any_initfn() should never set ARM_FEATURE_AARCH64, Peter Maydell, 2014/06/09
- [Qemu-devel] [PULL 07/20] target-arm: Allow 3reg_wide undefreq to encode more bad size options, Peter Maydell, 2014/06/09
- [Qemu-devel] [PULL 08/20] target-arm: add support for v8 VMULL.P64 instruction, Peter Maydell, 2014/06/09
- [Qemu-devel] [PULL 17/20] target-arm: A64: Implement 3-register SHA instructions, Peter Maydell, 2014/06/09