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[Qemu-devel] [PATCH v3 16/32] target-arm: add SDER definition
From: |
Fabian Aggeler |
Subject: |
[Qemu-devel] [PATCH v3 16/32] target-arm: add SDER definition |
Date: |
Wed, 11 Jun 2014 01:54:58 +0200 |
From: Sergey Fedorov <address@hidden>
Signed-off-by: Sergey Fedorov <address@hidden>
Signed-off-by: Fabian Aggeler <address@hidden>
---
target-arm/cpu.h | 1 +
target-arm/helper.c | 3 +++
2 files changed, 4 insertions(+)
diff --git a/target-arm/cpu.h b/target-arm/cpu.h
index bc9edaa..c76a31c 100644
--- a/target-arm/cpu.h
+++ b/target-arm/cpu.h
@@ -182,6 +182,7 @@ typedef struct CPUARMState {
uint64_t c1_coproc; /* Coprocessor access register. */
uint32_t c1_xscaleauxcr; /* XScale auxiliary control register. */
uint32_t c1_scr; /* secure config register. */
+ uint32_t c1_sder; /* Secure debug enable register. */
uint32_t c1_nsacr; /* Non-secure access control register. */
uint64_t ttbr0_el1; /* MMU translation table base 0. */
uint64_t ttbr1_el1; /* MMU translation table base 1. */
diff --git a/target-arm/helper.c b/target-arm/helper.c
index 9671f9f..4bf203e 100644
--- a/target-arm/helper.c
+++ b/target-arm/helper.c
@@ -2279,6 +2279,9 @@ static const ARMCPRegInfo security_cp_reginfo[] = {
{ .name = "SCR", .cp = 15, .crn = 1, .crm = 1, .opc1 = 0, .opc2 = 0,
.access = PL3_RW, .fieldoffset = offsetof(CPUARMState, cp15.scr_el3),
.resetvalue = 0, },
+ { .name = "SDER", .cp = 15, .crn = 1, .crm = 1, .opc1 = 0, .opc2 = 1,
+ .access = PL3_RW, .resetvalue = 0,
+ .fieldoffset = offsetof(CPUARMState, cp15.c1_sder) },
{ .name = "NSACR", .cp = 15, .crn = 1, .crm = 1, .opc1 = 0, .opc2 = 2,
.access = PL3_RW | PL1_R, .resetvalue = 0,
.writefn = nsacr_write, .readfn = nsacr_read,
--
1.8.3.2
- Re: [Qemu-devel] [PATCH v3 11/32] target-arm: add async excp target_el&mode function, (continued)
Re: [Qemu-devel] [PATCH v3 04/32] target-arm: add arm_is_secure() function, Edgar E. Iglesias, 2014/06/17
[Qemu-devel] [PATCH v3 10/32] target-arm: extend Aarch64 SCR.{FIQ|IRQ} handling, Fabian Aggeler, 2014/06/10
[Qemu-devel] [PATCH v3 16/32] target-arm: add SDER definition,
Fabian Aggeler <=
[Qemu-devel] [PATCH v3 17/32] target-arm: add MVBAR support, Fabian Aggeler, 2014/06/10
[Qemu-devel] [PATCH v3 18/32] target-arm: add macros to access banked registers, Fabian Aggeler, 2014/06/10
[Qemu-devel] [PATCH v3 19/32] target-arm: insert Aarch32 cpregs twice into hashtable, Fabian Aggeler, 2014/06/10
[Qemu-devel] [PATCH v3 20/32] target-arm: arrayfying fieldoffset for banking, Fabian Aggeler, 2014/06/10
[Qemu-devel] [PATCH v3 21/32] target-arm: add SCTLR_EL3 and make SCTLR banked, Fabian Aggeler, 2014/06/10