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Re: [Qemu-devel] [PATCH v2 14/22] target-mips: add Addressing and PC-rel
From: |
Peter Maydell |
Subject: |
Re: [Qemu-devel] [PATCH v2 14/22] target-mips: add Addressing and PC-relative instructions |
Date: |
Tue, 24 Jun 2014 15:54:30 +0100 |
On 24 June 2014 15:24, Richard Henderson <address@hidden> wrote:
> On 06/24/2014 03:00 AM, Peter Maydell wrote:
>> This is undefined behaviour in C because of the shift into
>> the sign bit. Better to shift first and then signextend:
>>
>> offset = sextract32(ctx->opcode << 3, 0, 21);
>
> Not true. Because we know from the extract that the value has
> 13 copies of the sign bit. Shifting by 3 isn't going to cause
> problems. It's shifting a *different* bit into the sign position
> that's (one's compliment) undefined.
C99 6.5.7 says that for E1 << E2, "If E1 has a signed type
and nonnegative value, and E1 * 2^E2 is representable in
the result type, then that is the resulting value; otherwise,
the behavior is undefined." As I read that, shifting
any negative value is undefined, as well as shifting
a 1 into the sign bit.
> PS: Honestly, all these compilers/sanitizers should grow a "No One's
> Compliment" switch to disable all the stupid stuff.
Heartily agreed. Unfortunately until they do, I don't trust
the compiler not to decide it can be fantastically clever
and speed up specmark by 0.00003% if it breaks the 2s
complement behaviour for signed shifts.
thanks
-- PMM
[Qemu-devel] [PATCH v2 18/22] target-mips: do not allow Status.FR=0 mode in 64-bit FPU, Leon Alrae, 2014/06/11
[Qemu-devel] [PATCH v2 17/22] target-mips: add new Floating Point Comparison instructions, Leon Alrae, 2014/06/11
[Qemu-devel] [PATCH v2 16/22] target-mips: add new Floating Point instructions, Leon Alrae, 2014/06/11
[Qemu-devel] [PATCH v2 19/22] target-mips: remove JR, BLTZAL, BGEZAL and add NAL, BAL instructions, Leon Alrae, 2014/06/11
[Qemu-devel] [PATCH v2 21/22] target-mips: use pointers referring to appropriate decoding function, Leon Alrae, 2014/06/11