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[Qemu-devel] [PATCH v4 12/33] target-arm: use dedicated target_el functi
From: |
greg . bellows |
Subject: |
[Qemu-devel] [PATCH v4 12/33] target-arm: use dedicated target_el function |
Date: |
Mon, 30 Jun 2014 18:09:12 -0500 |
From: Fabian Aggeler <address@hidden>
Signed-off-by: Fabian Aggeler <address@hidden>
Signed-off-by: Greg Bellows <address@hidden>
---
target-arm/helper.c | 24 ++++++------------------
1 file changed, 6 insertions(+), 18 deletions(-)
diff --git a/target-arm/helper.c b/target-arm/helper.c
index 4233ae3..456b7e7 100644
--- a/target-arm/helper.c
+++ b/target-arm/helper.c
@@ -3444,14 +3444,10 @@ unsigned int arm_excp_target_el(CPUState *cs, unsigned
int excp_idx)
CPUARMState *env = cs->env_ptr;
unsigned int cur_el = arm_current_pl(env);
unsigned int target_el = 1;
+ unsigned int target_mode;
bool route_to_el2 = false;
- /* FIXME: Use actual secure state. */
- bool secure = false;
- if (!env->aarch64) {
- /* TODO: Add EL2 and 3 exception handling for AArch32. */
- return 1;
- }
+ bool secure = arm_is_secure(env);
if (!secure
&& arm_feature(env, ARM_FEATURE_EL2)
@@ -3473,18 +3469,10 @@ unsigned int arm_excp_target_el(CPUState *cs, unsigned
int excp_idx)
}
break;
case EXCP_FIQ:
- case EXCP_IRQ: {
- const uint64_t hcr_mask = excp_idx == EXCP_FIQ ? HCR_FMO : HCR_IMO;
- const uint32_t scr_mask = excp_idx == EXCP_FIQ ? SCR_FIQ : SCR_IRQ;
-
- if (!secure && (env->cp15.hcr_el2 & hcr_mask)) {
- target_el = 2;
- }
- if (env->cp15.scr_el3 & scr_mask) {
- target_el = 3;
- }
- break;
- }
+ case EXCP_IRQ:
+ target_el = arm_phys_excp_target_el(cs, &target_mode, excp_idx,
+ cur_el, secure);
+ break;
case EXCP_VIRQ:
case EXCP_VFIQ:
target_el = 1;
--
1.8.3.2
- [Qemu-devel] [PATCH v4 04/33] target-arm: add arm_is_secure() function, (continued)
- [Qemu-devel] [PATCH v4 04/33] target-arm: add arm_is_secure() function, greg . bellows, 2014/06/30
- [Qemu-devel] [PATCH v4 03/33] target-arm: increase arrays of registers R13 & R14, greg . bellows, 2014/06/30
- [Qemu-devel] [PATCH v4 05/33] target-arm: reject switching to monitor mode, greg . bellows, 2014/06/30
- [Qemu-devel] [PATCH v4 01/33] target-arm: add cpu feature EL3 to CPUs with Security Extensions, greg . bellows, 2014/06/30
- [Qemu-devel] [PATCH v4 06/33] target-arm: make arm_current_pl() return PL3, greg . bellows, 2014/06/30
- [Qemu-devel] [PATCH v4 07/33] target-arm: add non-secure Translation Block flag, greg . bellows, 2014/06/30
- [Qemu-devel] [PATCH v4 08/33] target-arm: A32: Emulate the SMC instruction, greg . bellows, 2014/06/30
- [Qemu-devel] [PATCH v4 09/33] target-arm: extend Aarch32 async excp masking, greg . bellows, 2014/06/30
- [Qemu-devel] [PATCH v4 10/33] target-arm: extend Aarch64 SCR.{FIQ|IRQ} handling, greg . bellows, 2014/06/30
- [Qemu-devel] [PATCH v4 11/33] target-arm: add async excp target_el&mode function, greg . bellows, 2014/06/30
- [Qemu-devel] [PATCH v4 12/33] target-arm: use dedicated target_el function,
greg . bellows <=
- [Qemu-devel] [PATCH v4 13/33] target-arm: implement IRQ/FIQ routing to Monitor mode, greg . bellows, 2014/06/30
- [Qemu-devel] [PATCH v4 14/33] target-arm: Respect SCR.FW, SCR.AW and SCTLR.NMFI, greg . bellows, 2014/06/30
- [Qemu-devel] [PATCH v4 15/33] target-arm: add NSACR register, greg . bellows, 2014/06/30
- [Qemu-devel] [PATCH v4 16/33] target-arm: add SDER definition, greg . bellows, 2014/06/30
- [Qemu-devel] [PATCH v4 17/33] target-arm: add MVBAR support, greg . bellows, 2014/06/30
- [Qemu-devel] [PATCH v4 18/33] target-arm: add macros to access banked registers, greg . bellows, 2014/06/30
- [Qemu-devel] [PATCH v4 19/33] target-arm: insert Aarch32 cpregs twice into hashtable, greg . bellows, 2014/06/30
- [Qemu-devel] [PATCH v4 20/33] target-arm: arrayfying fieldoffset for banking, greg . bellows, 2014/06/30
- [Qemu-devel] [PATCH v4 21/33] target-arm: add SCTLR_EL3 and make SCTLR banked, greg . bellows, 2014/06/30
- [Qemu-devel] [PATCH v4 22/33] target-arm: make CSSELR banked, greg . bellows, 2014/06/30