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[Qemu-devel] [PATCH v4 28/33] target-arm: make DFSR banked
From: |
greg . bellows |
Subject: |
[Qemu-devel] [PATCH v4 28/33] target-arm: make DFSR banked |
Date: |
Mon, 30 Jun 2014 18:09:28 -0500 |
From: Fabian Aggeler <address@hidden>
When EL3 is running in Aarch32 (or ARMv7 with Security Extensions)
DFSR has a secure and a non-secure instance.
Signed-off-by: Fabian Aggeler <address@hidden>
Signed-off-by: Greg Bellows <address@hidden>
---------------
v3 -> v4
- Reverted esr/dfsr back to array-based notation as a union with v7 naming.
Signed-off-by: Greg Bellows <address@hidden>
---
target-arm/cpu.h | 10 +++++++++-
target-arm/helper.c | 7 ++++---
2 files changed, 13 insertions(+), 4 deletions(-)
diff --git a/target-arm/cpu.h b/target-arm/cpu.h
index 7935915..872b42d 100644
--- a/target-arm/cpu.h
+++ b/target-arm/cpu.h
@@ -266,7 +266,15 @@ typedef struct CPUARMState {
uint32_t ifsr32_el2;
};
};
- uint64_t esr_el[4];
+ union {
+ struct {
+ uint64_t _unused_dfsr;
+ uint64_t dfsr_ns;
+ uint64_t hsr;
+ uint64_t dfsr_s;
+ };
+ uint64_t esr_el[4];
+ };
uint32_t c6_region[8]; /* MPU base/size registers. */
uint64_t far_el[4]; /* Fault address registers. */
uint64_t par_el1; /* Translation result. */
diff --git a/target-arm/helper.c b/target-arm/helper.c
index fea2d59..fa3ae3a 100644
--- a/target-arm/helper.c
+++ b/target-arm/helper.c
@@ -1503,7 +1503,8 @@ static void vmsa_ttbr_write(CPUARMState *env, const
ARMCPRegInfo *ri,
static const ARMCPRegInfo vmsa_cp_reginfo[] = {
{ .name = "DFSR", .cp = 15, .crn = 5, .crm = 0, .opc1 = 0, .opc2 = 0,
.access = PL1_RW, .type = ARM_CP_NO_MIGRATE,
- .fieldoffset = offsetoflow32(CPUARMState, cp15.esr_el[1]),
+ .bank_fieldoffsets = { offsetoflow32(CPUARMState, cp15.dfsr_s),
+ offsetoflow32(CPUARMState, cp15.dfsr_ns) },
.resetfn = arm_cp_reset_ignore, },
{ .name = "IFSR", .cp = 15, .crn = 5, .crm = 0, .opc1 = 0, .opc2 = 1,
.access = PL1_RW, .resetvalue = 0,
@@ -3882,11 +3883,11 @@ void arm_cpu_do_interrupt(CPUState *cs)
offset = 4;
break;
case EXCP_DATA_ABORT:
- env->cp15.esr_el[1] = env->exception.fsr;
+ A32_BANKED_CURRENT_REG_SET(env, dfsr, env->exception.fsr);
env->cp15.far_el[1] = deposit64(env->cp15.far_el[1], 0, 32,
env->exception.vaddress);
qemu_log_mask(CPU_LOG_INT, "...with DFSR 0x%x DFAR 0x%x\n",
- (uint32_t)env->cp15.esr_el[1],
+ env->exception.fsr,
(uint32_t)env->exception.vaddress);
new_mode = ARM_CPU_MODE_ABT;
addr = 0x10;
--
1.8.3.2
- [Qemu-devel] [PATCH v4 18/33] target-arm: add macros to access banked registers, (continued)
- [Qemu-devel] [PATCH v4 18/33] target-arm: add macros to access banked registers, greg . bellows, 2014/06/30
- [Qemu-devel] [PATCH v4 19/33] target-arm: insert Aarch32 cpregs twice into hashtable, greg . bellows, 2014/06/30
- [Qemu-devel] [PATCH v4 20/33] target-arm: arrayfying fieldoffset for banking, greg . bellows, 2014/06/30
- [Qemu-devel] [PATCH v4 21/33] target-arm: add SCTLR_EL3 and make SCTLR banked, greg . bellows, 2014/06/30
- [Qemu-devel] [PATCH v4 22/33] target-arm: make CSSELR banked, greg . bellows, 2014/06/30
- [Qemu-devel] [PATCH v4 23/33] target-arm: add TTBR0_EL3 and make TTBR0/1 banked, greg . bellows, 2014/06/30
- [Qemu-devel] [PATCH v4 24/33] target-arm: add TCR_EL3 and make TTBCR banked, greg . bellows, 2014/06/30
- [Qemu-devel] [PATCH v4 25/33] target-arm: make c2_mask and c2_base_mask banked, greg . bellows, 2014/06/30
- [Qemu-devel] [PATCH v4 26/33] target-arm: make DACR banked, greg . bellows, 2014/06/30
- [Qemu-devel] [PATCH v4 27/33] target-arm: make IFSR banked, greg . bellows, 2014/06/30
- [Qemu-devel] [PATCH v4 28/33] target-arm: make DFSR banked,
greg . bellows <=
- [Qemu-devel] [PATCH v4 29/33] target-arm: make IFAR/DFAR banked, greg . bellows, 2014/06/30
- [Qemu-devel] [PATCH v4 32/33] target-arm: make c13 cp regs banked (FCSEIDR, ...), greg . bellows, 2014/06/30
- [Qemu-devel] [PATCH v4 33/33] target-arm: Limit migration of duplicate CP regs, greg . bellows, 2014/06/30
- [Qemu-devel] [PATCH v4 31/33] target-arm: make VBAR banked, greg . bellows, 2014/06/30
- [Qemu-devel] [PATCH v4 30/33] target-arm: make PAR banked, greg . bellows, 2014/06/30