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Re: [Qemu-devel] [PATCH v2 06/15] target-tricore: Add instructions of SR
From: |
Richard Henderson |
Subject: |
Re: [Qemu-devel] [PATCH v2 06/15] target-tricore: Add instructions of SRC opcode format |
Date: |
Tue, 15 Jul 2014 08:42:48 -0700 |
User-agent: |
Mozilla/5.0 (X11; Linux x86_64; rv:24.0) Gecko/20100101 Thunderbird/24.6.0 |
On 07/15/2014 06:19 AM, Bastian Koppelmann wrote:
>
>>> + tcg_gen_addi_tl(cpu_gpr_d[r1], cpu_gpr_d[r1], const4);
>> Are you planning to come back to implement V and AV bits later?
> Would you recommend implementing this as a helper? It seems rather complex.
> Especially with half-word and byte arithmetic. On the other hand the
> instructions using this are common and would benefit from open-coding it in
> TCG.
The halfword and byte insns probably require a helper. It's certainly going to
be worth while open coding the full word operations.
Ideally we'd be able to use vector instructions on the host, but we'd need
serious enhancements to TCG in order to implement that.
When the implementation of an insn requires more than, say, a dozen insns, or
requires any branching at all, then I believe we're better off sharing the code
with a helper. This is because the real compiler is significantly better than
TCG at generating code across basic blocks, and the reduction in icache usage.
r~
- [Qemu-devel] [PATCH v2 00/15] TriCore architecture guest implementation, Bastian Koppelmann, 2014/07/14
- [Qemu-devel] [PATCH v2 04/15] target-tricore: Add initialization for translation and activate target, Bastian Koppelmann, 2014/07/14
- [Qemu-devel] [PATCH v2 02/15] target-tricore: Add board for systemmode, Bastian Koppelmann, 2014/07/14
- [Qemu-devel] [PATCH v2 05/15] target-tricore: Add masks and opcodes for decoding, Bastian Koppelmann, 2014/07/14
- [Qemu-devel] [PATCH v2 13/15] target-tricore: Add instructions of SC opcode format, Bastian Koppelmann, 2014/07/14
- [Qemu-devel] [PATCH v2 07/15] target-tricore: Add instructions of SRR opcode format, Bastian Koppelmann, 2014/07/14
- [Qemu-devel] [PATCH v2 09/15] target-tricore: Add instructions of SRRS and SLRO opcode format, Bastian Koppelmann, 2014/07/14
- [Qemu-devel] [PATCH v2 11/15] target-tricore: Add instructions of SBC and SBRN opcode format, Bastian Koppelmann, 2014/07/14