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[Qemu-devel] [PATCH 3/3] arm_gic: GICD_ICFGR: Do not force edge-triggere
From: |
Adam Lackorzynski |
Subject: |
[Qemu-devel] [PATCH 3/3] arm_gic: GICD_ICFGR: Do not force edge-triggered PPIs |
Date: |
Sun, 3 Aug 2014 10:53:47 +0200 |
Using GICD_ICFGR for PPIs forces PPIs to edge-triggered mode, although they
have been initialised to level-triggered. This affects all interrupts
covered by the write access. Change the handling of PPIs to not force a
specific mode. It is implementation defined whether setting the mode of PPIs
is supported.
Signed-off-by: Adam Lackorzynski <address@hidden>
---
hw/intc/arm_gic.c | 2 --
1 file changed, 2 deletions(-)
diff --git a/hw/intc/arm_gic.c b/hw/intc/arm_gic.c
index cd6e6ea..066a7f2 100644
--- a/hw/intc/arm_gic.c
+++ b/hw/intc/arm_gic.c
@@ -558,8 +558,6 @@ static void gic_dist_writeb(void *opaque, hwaddr offset,
irq = (offset - 0xc00) * 4 + GIC_BASE_IRQ;
if (irq >= s->num_irq)
goto bad_reg;
- if (irq < GIC_INTERNAL)
- value |= 0xaa;
for (i = 0; i < 4; i++) {
if (value & (1 << (i * 2))) {
GIC_SET_MODEL(irq + i);
--
2.0.1