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[Qemu-devel] [PATCH 11/11] target-arm: Implement MDSCR_EL1 as having sta
From: |
Peter Maydell |
Subject: |
[Qemu-devel] [PATCH 11/11] target-arm: Implement MDSCR_EL1 as having state |
Date: |
Fri, 8 Aug 2014 13:18:14 +0100 |
Now that all the new code to support single-stepping is in
place, wire up the guest-visible MDSCR_EL1, so the guest
can enable single-stepping.
Signed-off-by: Peter Maydell <address@hidden>
---
target-arm/helper.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/target-arm/helper.c b/target-arm/helper.c
index f981569..2a77c97 100644
--- a/target-arm/helper.c
+++ b/target-arm/helper.c
@@ -2204,7 +2204,9 @@ static const ARMCPRegInfo debug_cp_reginfo[] = {
*/
{ .name = "MDSCR_EL1", .state = ARM_CP_STATE_BOTH,
.cp = 14, .opc0 = 2, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 2,
- .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
+ .access = PL1_RW,
+ .fieldoffset = offsetof(CPUARMState, cp15.mdscr_el1),
+ .resetvalue = 0 },
/* We define a dummy WI OSLAR_EL1, because Linux writes to it. */
{ .name = "OSLAR_EL1", .state = ARM_CP_STATE_BOTH,
.cp = 14, .opc0 = 2, .opc1 = 0, .crn = 1, .crm = 0, .opc2 = 4,
--
1.9.1
- [Qemu-devel] [PATCH 04/11] target-arm: Adjust debug ID registers per-CPU, (continued)
[Qemu-devel] [PATCH 02/11] target-arm: Allow STATE_BOTH reginfo descriptions for more than cp14, Peter Maydell, 2014/08/08
[Qemu-devel] [PATCH 10/11] target-arm: Implement ARMv8 single-stepping for AArch32 code, Peter Maydell, 2014/08/08
[Qemu-devel] [PATCH 11/11] target-arm: Implement MDSCR_EL1 as having state,
Peter Maydell <=
Re: [Qemu-devel] [PATCH 00/11] target-arm: Implement ARMv8 debug single-stepping, Peter Maydell, 2014/08/18