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[Qemu-devel] [V2 PATCH 7/8] target-ppc: Bug Fix: srawi
From: |
Tom Musta |
Subject: |
[Qemu-devel] [V2 PATCH 7/8] target-ppc: Bug Fix: srawi |
Date: |
Tue, 12 Aug 2014 08:45:09 -0500 |
For 64 bit implementations, the special case of a shift by zero
should result in the sign extension of the least significant 32 bits
of the source GPR (not a direct copy of the 64 bit source GPR).
Example:
R3 A6212433228F41DC
srawi 3,3,0
R3 expected : 00000000228F41DC
R3 actual : A6212433228F41DC (without this patch)
Signed-off-by: Tom Musta <address@hidden>
---
target-ppc/translate.c | 2 +-
1 files changed, 1 insertions(+), 1 deletions(-)
diff --git a/target-ppc/translate.c b/target-ppc/translate.c
index 4904665..61fa42d 100644
--- a/target-ppc/translate.c
+++ b/target-ppc/translate.c
@@ -1941,7 +1941,7 @@ static void gen_srawi(DisasContext *ctx)
TCGv dst = cpu_gpr[rA(ctx->opcode)];
TCGv src = cpu_gpr[rS(ctx->opcode)];
if (sh == 0) {
- tcg_gen_mov_tl(dst, src);
+ tcg_gen_ext32s_tl(dst, src);
tcg_gen_movi_tl(cpu_ca, 0);
} else {
TCGv t0;
--
1.7.1
- [Qemu-devel] [V2 PATCH 0/8] target-ppc: Bug Fixes for 64 Bit FXU Instructions, Tom Musta, 2014/08/12
- [Qemu-devel] [V2 PATCH 1/8] target-ppc: Bug Fix: rlwinm, Tom Musta, 2014/08/12
- [Qemu-devel] [V2 PATCH 2/8] target-ppc: Bug Fix: rlwnm, Tom Musta, 2014/08/12
- [Qemu-devel] [V2 PATCH 3/8] target-ppc: Bug Fix: rlwimi, Tom Musta, 2014/08/12
- [Qemu-devel] [V2 PATCH 4/8] target-ppc: Bug Fix: mullw, Tom Musta, 2014/08/12
- [Qemu-devel] [V2 PATCH 5/8] target-ppc: Bug Fix: mullwo, Tom Musta, 2014/08/12
- [Qemu-devel] [V2 PATCH 6/8] target-ppc: Bug Fix: mulldo OV Detection, Tom Musta, 2014/08/12
- [Qemu-devel] [V2 PATCH 7/8] target-ppc: Bug Fix: srawi,
Tom Musta <=
- [Qemu-devel] [V2 PATCH 8/8] target-ppc: Bug Fix: srad, Tom Musta, 2014/08/12
- Re: [Qemu-devel] [V2 PATCH 0/8] target-ppc: Bug Fixes for 64 Bit FXU Instructions, Alexander Graf, 2014/08/12