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[Qemu-devel] [PULL 15/19] arm: cortex-a9: Fix cache-line size and associ
From: |
Peter Maydell |
Subject: |
[Qemu-devel] [PULL 15/19] arm: cortex-a9: Fix cache-line size and associativity |
Date: |
Tue, 19 Aug 2014 19:09:40 +0100 |
From: Peter Crosthwaite <address@hidden>
For A9, The cache associativity is 4 and the lines size is 32B.
Self identify in CCSIDR accordingly. Cache size remains at 16k.
QEMU doesn't emulate caches, but we should still report the correct
cache-line size to the guest. Some guests (like u-boot) complain if
the cache-line size mismatches a requested flush or invalidate
operation.
Signed-off-by: Peter Crosthwaite <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>
---
target-arm/cpu.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/target-arm/cpu.c b/target-arm/cpu.c
index e27cca2..8199f32 100644
--- a/target-arm/cpu.c
+++ b/target-arm/cpu.c
@@ -715,8 +715,8 @@ static void cortex_a9_initfn(Object *obj)
cpu->id_isar4 = 0x00111142;
cpu->dbgdidr = 0x35141000;
cpu->clidr = (1 << 27) | (1 << 24) | 3;
- cpu->ccsidr[0] = 0xe00fe015; /* 16k L1 dcache. */
- cpu->ccsidr[1] = 0x200fe015; /* 16k L1 icache. */
+ cpu->ccsidr[0] = 0xe00fe019; /* 16k L1 dcache. */
+ cpu->ccsidr[1] = 0x200fe019; /* 16k L1 icache. */
define_arm_cp_regs(cpu, cortexa9_cp_reginfo);
}
--
1.9.1
- [Qemu-devel] [PULL 00/19] target-arm queue, Peter Maydell, 2014/08/19
- [Qemu-devel] [PULL 18/19] arm: armv7m: Rename address_space_mem -> system_memory, Peter Maydell, 2014/08/19
- [Qemu-devel] [PULL 17/19] aarch64: Allow -kernel option to take a gzip-compressed kernel., Peter Maydell, 2014/08/19
- [Qemu-devel] [PULL 15/19] arm: cortex-a9: Fix cache-line size and associativity,
Peter Maydell <=
- [Qemu-devel] [PULL 13/19] target-arm: Rename QEMU PSCI v0.1 definitions, Peter Maydell, 2014/08/19
- [Qemu-devel] [PULL 12/19] target-arm: Implement MDSCR_EL1 as having state, Peter Maydell, 2014/08/19
- [Qemu-devel] [PULL 11/19] target-arm: Implement ARMv8 single-stepping for AArch32 code, Peter Maydell, 2014/08/19
- [Qemu-devel] [PULL 10/19] target-arm: Implement ARMv8 single-step handling for A64 code, Peter Maydell, 2014/08/19
- [Qemu-devel] [PULL 14/19] arm/virt: Use PSCI v0.2 function IDs in the DT when KVM uses PSCI v0.2, Peter Maydell, 2014/08/19
- [Qemu-devel] [PULL 16/19] loader: Add load_image_gzipped function., Peter Maydell, 2014/08/19
- [Qemu-devel] [PULL 09/19] target-arm: A64: Avoid duplicate exit_tb(0) in non-linked goto_tb, Peter Maydell, 2014/08/19
- [Qemu-devel] [PULL 08/19] target-arm: Set PSTATE.SS correctly on exception return from AArch64, Peter Maydell, 2014/08/19
- [Qemu-devel] [PULL 06/19] target-arm: Don't allow AArch32 to access RES0 CPSR bits, Peter Maydell, 2014/08/19
- [Qemu-devel] [PULL 04/19] target-arm: Provide both 32 and 64 bit versions of debug registers, Peter Maydell, 2014/08/19