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[Qemu-devel] [PATCH target-arm v4 2/7] arm: Implement PMCCNTR 32b read-m
From: |
Peter Crosthwaite |
Subject: |
[Qemu-devel] [PATCH target-arm v4 2/7] arm: Implement PMCCNTR 32b read-modify-write |
Date: |
Mon, 25 Aug 2014 21:10:16 -0700 |
The register is now 64bit, however a 32 bit write to the register
should leave the higher bits unchanged. The open coded write handler
does not implement this, so we need to read-modify-write accordingly.
Signed-off-by: Peter Crosthwaite <address@hidden>
---
target-arm/helper.c | 11 ++++++++++-
1 file changed, 10 insertions(+), 1 deletion(-)
diff --git a/target-arm/helper.c b/target-arm/helper.c
index 711ca12..0d2ee41 100644
--- a/target-arm/helper.c
+++ b/target-arm/helper.c
@@ -623,6 +623,15 @@ static void pmccntr_write(CPUARMState *env, const
ARMCPRegInfo *ri,
}
env->cp15.c15_ccnt = total_ticks - value;
}
+
+static void pmccntr_write32(CPUARMState *env, const ARMCPRegInfo *ri,
+ uint64_t value)
+{
+ uint64_t cur_val = pmccntr_read(env, NULL);
+
+ pmccntr_write(env, ri, deposit64(cur_val, 0, 32, value));
+}
+
#endif
static void pmcntenset_write(CPUARMState *env, const ARMCPRegInfo *ri,
@@ -754,7 +763,7 @@ static const ARMCPRegInfo v7_cp_reginfo[] = {
#ifndef CONFIG_USER_ONLY
{ .name = "PMCCNTR", .cp = 15, .crn = 9, .crm = 13, .opc1 = 0, .opc2 = 0,
.access = PL0_RW, .resetvalue = 0, .type = ARM_CP_IO,
- .readfn = pmccntr_read, .writefn = pmccntr_write,
+ .readfn = pmccntr_read, .writefn = pmccntr_write32,
.accessfn = pmreg_access },
#endif
{ .name = "PMXEVTYPER", .cp = 15, .crn = 9, .crm = 13, .opc1 = 0, .opc2 =
1,
--
2.1.0.1.g27b9230
- [Qemu-devel] [PATCH target-arm v4 0/7] target-arm: Extend PMCCNTR for ARMv8, Peter Crosthwaite, 2014/08/26
- [Qemu-devel] [PATCH target-arm v4 1/7] target-arm: Make the ARM PMCCNTR register 64-bit, Peter Crosthwaite, 2014/08/26
- [Qemu-devel] [PATCH target-arm v4 2/7] arm: Implement PMCCNTR 32b read-modify-write,
Peter Crosthwaite <=
- [Qemu-devel] [PATCH target-arm v4 3/7] target-arm: Implement PMCCNTR_EL0 and related registers, Peter Crosthwaite, 2014/08/26
- [Qemu-devel] [PATCH target-arm v4 4/7] target-arm: Add arm_ccnt_enabled function, Peter Crosthwaite, 2014/08/26
- [Qemu-devel] [PATCH target-arm v4 5/7] target-arm: Implement pmccntr_sync function, Peter Crosthwaite, 2014/08/26
- [Qemu-devel] [PATCH target-arm v4 6/7] target-arm: Remove old code and replace with new functions, Peter Crosthwaite, 2014/08/26
- [Qemu-devel] [PATCH target-arm v4 7/7] target-arm: Implement pmccfiltr_write function, Peter Crosthwaite, 2014/08/26
- Re: [Qemu-devel] [PATCH target-arm v4 0/7] target-arm: Extend PMCCNTR for ARMv8, Peter Maydell, 2014/08/29