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[Qemu-devel] [PATCH 14/17] ppc: introduce ppc_get_crf and ppc_set_crf
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From: |
Paolo Bonzini |
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Subject: |
[Qemu-devel] [PATCH 14/17] ppc: introduce ppc_get_crf and ppc_set_crf |
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Date: |
Thu, 28 Aug 2014 19:15:10 +0200 |
These two functions will group together four CR bits into a single
value, once we change the representation of condition registers.
Signed-off-by: Paolo Bonzini <address@hidden>
---
linux-user/elfload.c | 2 +-
linux-user/main.c | 2 +-
linux-user/signal.c | 4 ++--
monitor.c | 2 +-
target-ppc/cpu.h | 10 ++++++++++
target-ppc/excp_helper.c | 2 +-
target-ppc/fpu_helper.c | 6 ++++--
target-ppc/gdbstub.c | 4 ++--
target-ppc/int_helper.c | 16 ++++++++--------
target-ppc/kvm.c | 4 ++--
target-ppc/translate.c | 13 +++++++------
11 files changed, 39 insertions(+), 26 deletions(-)
diff --git a/linux-user/elfload.c b/linux-user/elfload.c
index bea803b..3769ae6 100644
--- a/linux-user/elfload.c
+++ b/linux-user/elfload.c
@@ -858,7 +858,7 @@ static void elf_core_copy_regs(target_elf_gregset_t *regs,
const CPUPPCState *en
(*regs)[37] = tswapreg(env->xer);
for (i = 0; i < ARRAY_SIZE(env->crf); i++) {
- ccr |= env->crf[i] << (32 - ((i + 1) * 4));
+ ccr |= ppc_get_crf(env, i) << (32 - ((i + 1) * 4));
}
(*regs)[38] = tswapreg(ccr);
}
diff --git a/linux-user/main.c b/linux-user/main.c
index 472a16d..152c031 100644
--- a/linux-user/main.c
+++ b/linux-user/main.c
@@ -1550,7 +1550,7 @@ static int do_store_exclusive(CPUPPCState *env)
}
}
}
- env->crf[0] = (stored << 1) | xer_so;
+ ppc_set_crf(env, 0, (stored << 1) | xer_so);
env->reserve_addr = (target_ulong)-1;
}
if (!segv) {
diff --git a/linux-user/signal.c b/linux-user/signal.c
index 26929c5..4f5d79f 100644
--- a/linux-user/signal.c
+++ b/linux-user/signal.c
@@ -4512,7 +4512,7 @@ static void save_user_regs(CPUPPCState *env, struct
target_mcontext *frame,
__put_user(env->xer, &frame->mc_gregs[TARGET_PT_XER]);
for (i = 0; i < ARRAY_SIZE(env->crf); i++) {
- ccr |= env->crf[i] << (32 - ((i + 1) * 4));
+ ccr |= ppc_get_crf(env, i) << (32 - ((i + 1) * 4));
}
__put_user(ccr, &frame->mc_gregs[TARGET_PT_CCR]);
@@ -4591,7 +4591,7 @@ static void restore_user_regs(CPUPPCState *env,
__get_user(ccr, &frame->mc_gregs[TARGET_PT_CCR]);
for (i = 0; i < ARRAY_SIZE(env->crf); i++) {
- env->crf[i] = (ccr >> (32 - ((i + 1) * 4))) & 0xf;
+ ppc_set_crf(env, i, (ccr >> (32 - ((i + 1) * 4))) & 0xf);
}
if (!sig) {
diff --git a/monitor.c b/monitor.c
index ec73dd4..97d72f4 100644
--- a/monitor.c
+++ b/monitor.c
@@ -2968,7 +2968,7 @@ static target_long monitor_get_ccr (const struct
MonitorDef *md, int val)
u = 0;
for (i = 0; i < 8; i++)
- u |= env->crf[i] << (32 - (4 * (i + 1)));
+ u |= ppc_get_crf(env, i) << (32 - (4 * (i + 1)));
return u;
}
diff --git a/target-ppc/cpu.h b/target-ppc/cpu.h
index c1cb27f..05c29b2 100644
--- a/target-ppc/cpu.h
+++ b/target-ppc/cpu.h
@@ -1198,6 +1198,16 @@ void ppc_tlb_invalidate_one (CPUPPCState *env,
target_ulong addr);
void store_fpscr(CPUPPCState *env, uint64_t arg, uint32_t mask);
+static inline uint32_t ppc_get_crf(const CPUPPCState *env, int i)
+{
+ return env->crf[i];
+}
+
+static inline void ppc_set_crf(CPUPPCState *env, int i, uint32_t val)
+{
+ env->crf[i] = val;
+}
+
static inline uint64_t ppc_dump_gpr(CPUPPCState *env, int gprn)
{
uint64_t gprv;
diff --git a/target-ppc/excp_helper.c b/target-ppc/excp_helper.c
index bf25d44..522fce4 100644
--- a/target-ppc/excp_helper.c
+++ b/target-ppc/excp_helper.c
@@ -504,7 +504,7 @@ static inline void powerpc_excp(PowerPCCPU *cpu, int
excp_model, int excp)
env->error_code);
}
#endif
- msr |= env->crf[0] << 28;
+ msr |= ppc_get_crf(env, 0) << 28;
msr |= env->error_code; /* key, D/I, S/L bits */
/* Set way using a LRU mechanism */
msr |= ((env->last_way + 1) & (env->nb_ways - 1)) << 17;
diff --git a/target-ppc/fpu_helper.c b/target-ppc/fpu_helper.c
index 0fe006a..1ccbcf3 100644
--- a/target-ppc/fpu_helper.c
+++ b/target-ppc/fpu_helper.c
@@ -1099,7 +1099,8 @@ void helper_fcmpu(CPUPPCState *env, uint64_t arg1,
uint64_t arg2,
env->fpscr &= ~(0x0F << FPSCR_FPRF);
env->fpscr |= (0x01 << FPSCR_FPRF) << ret;
- env->crf[crfD] = (1 << ret);
+ ppc_set_crf(env, crfD, 1 << ret);
+
if (unlikely(ret == CRF_SO
&& (float64_is_signaling_nan(farg1.d) ||
float64_is_signaling_nan(farg2.d)))) {
@@ -1130,7 +1131,8 @@ void helper_fcmpo(CPUPPCState *env, uint64_t arg1,
uint64_t arg2,
env->fpscr &= ~(0x0F << FPSCR_FPRF);
env->fpscr |= (0x01 << FPSCR_FPRF) << ret;
- env->crf[crfD] = (1 << ret);
+ ppc_set_crf(env, crfD, 1 << ret);
+
if (unlikely(ret == CRF_SO)) {
if (float64_is_signaling_nan(farg1.d) ||
float64_is_signaling_nan(farg2.d)) {
diff --git a/target-ppc/gdbstub.c b/target-ppc/gdbstub.c
index bad49ae..e0f340c 100644
--- a/target-ppc/gdbstub.c
+++ b/target-ppc/gdbstub.c
@@ -139,7 +139,7 @@ int ppc_cpu_gdb_read_register(CPUState *cs, uint8_t
*mem_buf, int n)
uint32_t cr = 0;
int i;
for (i = 0; i < ARRAY_SIZE(env->crf); i++) {
- cr |= env->crf[i] << (32 - ((i + 1) * 4));
+ cr |= ppc_get_crf(env, i) << (32 - ((i + 1) * 4));
}
gdb_get_reg32(mem_buf, cr);
break;
@@ -247,7 +247,7 @@ int ppc_cpu_gdb_write_register(CPUState *cs, uint8_t
*mem_buf, int n)
uint32_t cr = ldl_p(mem_buf);
int i;
for (i = 0; i < ARRAY_SIZE(env->crf); i++) {
- env->crf[i] = (cr >> (32 - ((i + 1) * 4))) & 0xF;
+ ppc_set_crf(env, i, (cr >> (32 - ((i + 1) * 4))) & 0xF);
}
break;
}
diff --git a/target-ppc/int_helper.c b/target-ppc/int_helper.c
index 5fa10c7..2287064 100644
--- a/target-ppc/int_helper.c
+++ b/target-ppc/int_helper.c
@@ -311,7 +311,7 @@ void helper_mtocrf(CPUPPCState *env, target_ulong cr,
uint32_t mask)
int i;
for (i = 7; i >= 0; i--) {
if (mask & 1) {
- env->crf[i] = cr & 0x0F;
+ ppc_set_crf(env, i, cr & 0x0F);
}
cr >>= 4;
mask >>= 1;
@@ -323,7 +323,7 @@ target_ulong helper_mfocrf(CPUPPCState *env)
uint32_t cr = 0;
int i;
for (i = 0; i < 8; i++) {
- cr |= env->crf[i] << (32 - (i + 1) * 4);
+ cr |= ppc_get_crf(env, i) << (32 - (i + 1) * 4);
}
return cr;
}
@@ -679,7 +679,7 @@ VCF(sx, int32_to_float32, s32)
none |= result; \
} \
if (record) { \
- env->crf[6] = ((all != 0) << 3) | ((none == 0) << 1); \
+ ppc_set_crf(env, 6, ((all != 0) << 3) | ((none == 0) << 1)); \
} \
}
#define VCMP(suffix, compare, element) \
@@ -725,7 +725,7 @@ VCMP(gtsd, >, s64)
none |= result; \
} \
if (record) { \
- env->crf[6] = ((all != 0) << 3) | ((none == 0) << 1); \
+ ppc_set_crf(env, 6, ((all != 0) << 3) | ((none == 0) << 1)); \
} \
}
#define VCMPFP(suffix, compare, order) \
@@ -759,7 +759,7 @@ static inline void vcmpbfp_internal(CPUPPCState *env,
ppc_avr_t *r,
}
}
if (record) {
- env->crf[6] = (all_in == 0) << 1;
+ ppc_set_crf(env, 6, (all_in == 0) << 1);
}
}
@@ -2580,7 +2580,7 @@ target_ulong helper_dlmzb(CPUPPCState *env, target_ulong
high,
for (mask = 0xFF000000; mask != 0; mask = mask >> 8) {
if ((high & mask) == 0) {
if (update_Rc) {
- env->crf[0] = 0x4;
+ ppc_set_crf(env, 0, 0x4);
}
goto done;
}
@@ -2589,7 +2589,7 @@ target_ulong helper_dlmzb(CPUPPCState *env, target_ulong
high,
for (mask = 0xFF000000; mask != 0; mask = mask >> 8) {
if ((low & mask) == 0) {
if (update_Rc) {
- env->crf[0] = 0x8;
+ ppc_set_crf(env, 0, 0x8);
}
goto done;
}
@@ -2597,7 +2597,7 @@ target_ulong helper_dlmzb(CPUPPCState *env, target_ulong
high,
}
i = 8;
if (update_Rc) {
- env->crf[0] = 0x2;
+ ppc_set_crf(env, 0, 0x2);
}
done:
env->xer = (env->xer & ~0x7F) | i;
diff --git a/target-ppc/kvm.c b/target-ppc/kvm.c
index 42718f7..a4eca17 100644
--- a/target-ppc/kvm.c
+++ b/target-ppc/kvm.c
@@ -795,7 +795,7 @@ int kvm_arch_put_registers(CPUState *cs, int level)
regs.cr = 0;
for (i = 0; i < 8; i++) {
- regs.cr |= (env->crf[i] & 15) << (4 * (7 - i));
+ regs.cr |= ppc_get_crf(env, i) << (4 * (7 - i));
}
ret = kvm_vcpu_ioctl(cs, KVM_SET_REGS, ®s);
@@ -914,7 +914,7 @@ int kvm_arch_get_registers(CPUState *cs)
cr = regs.cr;
for (i = 7; i >= 0; i--) {
- env->crf[i] = cr & 15;
+ ppc_set_crf(env->cr[i], cr & 15);
cr >>= 4;
}
diff --git a/target-ppc/translate.c b/target-ppc/translate.c
index 4ce7af4..1ed6a8f 100644
--- a/target-ppc/translate.c
+++ b/target-ppc/translate.c
@@ -11071,18 +11071,19 @@ void ppc_cpu_dump_state(CPUState *cs, FILE *f,
fprintf_function cpu_fprintf,
cpu_fprintf(f, "\n");
}
cpu_fprintf(f, "CR ");
- for (i = 0; i < 8; i++)
- cpu_fprintf(f, "%01x", env->crf[i]);
+ for (i = 0; i < 8; i++) {
+ cpu_fprintf(f, "%01x", ppc_get_crf(env, i));
+ }
cpu_fprintf(f, " [");
for (i = 0; i < 8; i++) {
char a = '-';
- if (env->crf[i] & 0x08)
+ if (ppc_get_crf(env, i) & 0x08)
a = 'L';
- else if (env->crf[i] & 0x04)
+ else if (ppc_get_crf(env, i) & 0x04)
a = 'G';
- else if (env->crf[i] & 0x02)
+ else if (ppc_get_crf(env, i) & 0x02)
a = 'E';
- cpu_fprintf(f, " %c%c", a, env->crf[i] & 0x01 ? 'O' : ' ');
+ cpu_fprintf(f, " %c%c", a, ppc_get_crf(env, i) & 0x01 ? 'O' : ' ');
}
cpu_fprintf(f, " ] RES " TARGET_FMT_lx "\n",
env->reserve_addr);
--
1.8.3.1
- [Qemu-devel] [PATCH 04/17] ppc: use ARRAY_SIZE in gdbstub.c, (continued)
- [Qemu-devel] [PATCH 04/17] ppc: use ARRAY_SIZE in gdbstub.c, Paolo Bonzini, 2014/08/28
- [Qemu-devel] [PATCH 03/17] ppc: fix monitor access to CR, Paolo Bonzini, 2014/08/28
- [Qemu-devel] [PATCH 05/17] ppc: use CRF_* in fpu_helper.c, Paolo Bonzini, 2014/08/28
- [Qemu-devel] [PATCH 06/17] ppc: use CRF_* in int_helper.c, Paolo Bonzini, 2014/08/28
- [Qemu-devel] [PATCH 07/17] ppc: fix result of DLMZB when no zero bytes are found, Paolo Bonzini, 2014/08/28
- [Qemu-devel] [PATCH 08/17] ppc: introduce helpers for mfocrf/mtocrf, Paolo Bonzini, 2014/08/28
- [Qemu-devel] [PATCH 09/17] ppc: reorganize gen_compute_fprf, Paolo Bonzini, 2014/08/28
- [Qemu-devel] [PATCH 10/17] ppc: introduce gen_op_mfcr/gen_op_mtcr, Paolo Bonzini, 2014/08/28
- [Qemu-devel] [PATCH 11/17] ppc: rename gen_set_cr6_from_fpscr, Paolo Bonzini, 2014/08/28
- [Qemu-devel] [PATCH 13/17] ppc: compute mask from BI using right shift, Paolo Bonzini, 2014/08/28
- [Qemu-devel] [PATCH 14/17] ppc: introduce ppc_get_crf and ppc_set_crf,
Paolo Bonzini <=
- [Qemu-devel] [PATCH 15/17] ppc: store CR registers in 32 1-bit registers, Paolo Bonzini, 2014/08/28
- [Qemu-devel] [PATCH 16/17] ppc: inline ppc_get_crf/ppc_set_crf when clearer, Paolo Bonzini, 2014/08/28
- [Qemu-devel] [PATCH 17/17] ppc: dump all 32 CR bits, Paolo Bonzini, 2014/08/28
- [Qemu-devel] [PATCH 12/17] ppc: use movcond for isel, Paolo Bonzini, 2014/08/28
- Re: [Qemu-devel] [RFT/RFH PATCH 00/16] PPC speedup patches for TCG, Tom Musta, 2014/08/28