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[Qemu-devel] [PULL 14/23] target-arm: Set DBGDSCR.MOE for debug exceptio
From: |
Peter Maydell |
Subject: |
[Qemu-devel] [PULL 14/23] target-arm: Set DBGDSCR.MOE for debug exceptions taken to AArch32 |
Date: |
Fri, 12 Sep 2014 14:23:45 +0100 |
For debug exceptions taken to AArch32 we have to set the
DBGDSCR.MOE (Method Of Entry) bits; we can identify the
kind of debug exception from the information in
exception.syndrome.
Signed-off-by: Peter Maydell <address@hidden>
---
target-arm/helper.c | 26 ++++++++++++++++++++++++++
1 file changed, 26 insertions(+)
diff --git a/target-arm/helper.c b/target-arm/helper.c
index b0d2424..30d8e60 100644
--- a/target-arm/helper.c
+++ b/target-arm/helper.c
@@ -3629,11 +3629,37 @@ void arm_cpu_do_interrupt(CPUState *cs)
uint32_t mask;
int new_mode;
uint32_t offset;
+ uint32_t moe;
assert(!IS_M(env));
arm_log_exception(cs->exception_index);
+ /* If this is a debug exception we must update the DBGDSCR.MOE bits */
+ switch (env->exception.syndrome >> ARM_EL_EC_SHIFT) {
+ case EC_BREAKPOINT:
+ case EC_BREAKPOINT_SAME_EL:
+ moe = 1;
+ break;
+ case EC_WATCHPOINT:
+ case EC_WATCHPOINT_SAME_EL:
+ moe = 10;
+ break;
+ case EC_AA32_BKPT:
+ moe = 3;
+ break;
+ case EC_VECTORCATCH:
+ moe = 5;
+ break;
+ default:
+ moe = 0;
+ break;
+ }
+
+ if (moe) {
+ env->cp15.mdscr_el1 = deposit64(env->cp15.mdscr_el1, 2, 4, moe);
+ }
+
/* TODO: Vectored interrupt controller. */
switch (cs->exception_index) {
case EXCP_UDEF:
--
1.9.1
- [Qemu-devel] [PULL 00/23] target-arm queue, Peter Maydell, 2014/09/12
- [Qemu-devel] [PULL 17/23] target-arm: Push legacy wildcard TLB ops back into v6, Peter Maydell, 2014/09/12
- [Qemu-devel] [PULL 09/23] exec.c: Record watchpoint fault address and direction, Peter Maydell, 2014/09/12
- [Qemu-devel] [PULL 18/23] target-arm: Make *IS TLB maintenance ops affect all CPUs, Peter Maydell, 2014/09/12
- [Qemu-devel] [PULL 23/23] hw/arm/boot: enable DTB support when booting ELF images, Peter Maydell, 2014/09/12
- [Qemu-devel] [PULL 11/23] target-arm: Implement setting of watchpoints, Peter Maydell, 2014/09/12
- [Qemu-devel] [PULL 14/23] target-arm: Set DBGDSCR.MOE for debug exceptions taken to AArch32,
Peter Maydell <=
- [Qemu-devel] [PULL 10/23] cpu-exec: Make debug_excp_handler a QOM CPU method, Peter Maydell, 2014/09/12
- [Qemu-devel] [PULL 16/23] target-arm: Implement minimal DBGVCR, OSDLR_EL1, MDCCSR_EL0, Peter Maydell, 2014/09/12
- [Qemu-devel] [PULL 15/23] target-arm: Remove comment about MDSCR_EL1 being dummy implementation, Peter Maydell, 2014/09/12
- [Qemu-devel] [PULL 19/23] hw/arm/virt: fix pl011 and pl031 irq flags, Peter Maydell, 2014/09/12
- [Qemu-devel] [PULL 05/23] target-arm: Fix broken indentation in arm_cpu_reest(), Peter Maydell, 2014/09/12
- [Qemu-devel] [PULL 07/23] exec.c: Relax restrictions on watchpoint length and alignment, Peter Maydell, 2014/09/12
- [Qemu-devel] [PULL 06/23] hw/arm/virt: Provide flash devices for boot ROMs, Peter Maydell, 2014/09/12
- [Qemu-devel] [PULL 12/23] target-arm: Move extended_addresses_enabled() to internals.h, Peter Maydell, 2014/09/12