Re: [Qemu-devel] [PATCH 03/14] target-ppc: use separate indices for various translation modes

[Richard Henderson]

On 09/16/2014 11:27 AM, Paolo Bonzini wrote:
> Il 16/09/2014 20:02, Richard Henderson ha scritto:
>> While we could probably fix this for ppc (using addis), it's not nearly so
>> easily fixable for arm -- without impacting performance anyway.
>>
>> Does 96k worth of TLBs really help that much?  Are all 12 of them actually
>> used?  Can we use a more complex encoding scheme for the mmu_idx and use 
>> less?
> 
> In practice, only 3 to 7 are---hence my original attempt at using some
> kind of FIFO caching:
> 
>    user mode, translation enabled
>    kernel mode, paging disabled
>    kernel mode, paging enabled
>    supervisor mode, paging disabled
>    supervisor mode, paging enabled
> 
> Plus perhaps kernel and supervisor mode with only data paging enabled.
> 
> You could lump together the IR!=0, DR!=0 cases, and flush that one TLB
> index if the IR/DR pair changes with respect to the last time.  This
> would use 6 indices.

I think I would prefer a solution that uses 6 indicies, as will not cause env
to overflow 64k, and not require that any tcg backends be updated.


r~