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Re: [Qemu-devel] [PATCH v3 03/21] target-mips: add SELEQZ and SELNEZ ins
From: |
James Hogan |
Subject: |
Re: [Qemu-devel] [PATCH v3 03/21] target-mips: add SELEQZ and SELNEZ instructions |
Date: |
Fri, 26 Sep 2014 13:03:38 +0100 |
User-agent: |
Mozilla/5.0 (X11; Linux x86_64; rv:24.0) Gecko/20100101 Thunderbird/24.5.0 |
Hi Leon,
On 27/06/14 16:21, Leon Alrae wrote:
> /* MIPS64 MIPS-3D ASE support. */
> #define I16 INSN_MIPS16
> @@ -1209,6 +1215,8 @@ const struct mips_opcode mips_builtin_opcodes[] =
> them first. The assemblers uses a hash table based on the
> instruction name anyhow. */
> /* name, args, match, mask, pinfo,
> membership */
> +{"seleqz", "d,v,t", 0x00000035, 0xfc0007ff, WR_d|RD_s|RD_t, 0,
> I32R6},
> +{"selnez", "d,v,t", 0x00000037, 0xfc0007ff, WR_d|RD_s|RD_t, 0,
> I32R6},
I don't think these need to be at the beginning of the table since
they're normal instructions, unlike "nop" for example which is encoded
as a "sll".
Otherwise
Reviewed-by: James Hogan <address@hidden>
Cheers
James
- Re: [Qemu-devel] [PATCH v3 03/21] target-mips: add SELEQZ and SELNEZ instructions,
James Hogan <=