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[Qemu-devel] [PATCH v5 23/33] target-arm: make c2_mask and c2_base_mask
From: |
Greg Bellows |
Subject: |
[Qemu-devel] [PATCH v5 23/33] target-arm: make c2_mask and c2_base_mask banked |
Date: |
Tue, 30 Sep 2014 16:49:35 -0500 |
From: Fabian Aggeler <address@hidden>
Since TTBCR is banked we will bank c2_mask and c2_base_mask too. This
avoids recalculating them on switches from secure to non-secure world.
Signed-off-by: Fabian Aggeler <address@hidden>
Signed-off-by: Greg Bellows <address@hidden>
----------
v4 -> v5
- Changed c2_mask updates to use the TTBCR cpreg bank flag for selcting the
secure bank instead of the A32_BANKED_CURRENT macro. This more accurately
chooses the correct bank matching that of the TTBCR being accessed.
---
target-arm/cpu.h | 10 ++++++++--
target-arm/helper.c | 24 ++++++++++++++++++------
2 files changed, 26 insertions(+), 8 deletions(-)
diff --git a/target-arm/cpu.h b/target-arm/cpu.h
index 477c219..54bce55 100644
--- a/target-arm/cpu.h
+++ b/target-arm/cpu.h
@@ -231,8 +231,14 @@ typedef struct CPUARMState {
uint64_t tcr_el3;
};
};
- uint32_t c2_mask; /* MMU translation table base selection mask. */
- uint32_t c2_base_mask; /* MMU translation table base 0 mask. */
+ struct { /* MMU translation table base selection mask. */
+ uint32_t c2_mask_ns;
+ uint32_t c2_mask_s;
+ };
+ struct { /* MMU translation table base 0 mask. */
+ uint32_t c2_base_mask_ns;
+ uint32_t c2_base_mask_s;
+ };
uint32_t c2_data; /* MPU data cachable bits. */
uint32_t c2_insn; /* MPU instruction cachable bits. */
uint32_t c3; /* MMU domain access control register
diff --git a/target-arm/helper.c b/target-arm/helper.c
index bdb76e0..a77ab95 100644
--- a/target-arm/helper.c
+++ b/target-arm/helper.c
@@ -1597,8 +1597,14 @@ static void vmsa_ttbcr_raw_write(CPUARMState *env, const
ARMCPRegInfo *ri,
* and the c2_mask and c2_base_mask values are meaningless.
*/
raw_write(env, ri, value);
- env->cp15.c2_mask = ~(((uint32_t)0xffffffffu) >> maskshift);
- env->cp15.c2_base_mask = ~((uint32_t)0x3fffu >> maskshift);
+
+ /* Update the masks corresponding to the the TTBCR bank being written */
+ A32_BANKED_REG_SET(env, c2_mask,
+ ((ri->type & ARM_CP_BANK_S) == ARM_CP_BANK_S),
+ ~(((uint32_t)0xffffffffu) >> maskshift));
+ A32_BANKED_REG_SET(env, c2_base_mask,
+ ((ri->type & ARM_CP_BANK_S) == ARM_CP_BANK_S),
+ ~((uint32_t)0x3fffu >> maskshift));
}
static void vmsa_ttbcr_write(CPUARMState *env, const ARMCPRegInfo *ri,
@@ -1617,9 +1623,15 @@ static void vmsa_ttbcr_write(CPUARMState *env, const
ARMCPRegInfo *ri,
static void vmsa_ttbcr_reset(CPUARMState *env, const ARMCPRegInfo *ri)
{
- env->cp15.c2_base_mask = 0xffffc000u;
+ /* Rest both the TTBCR as well as the masks corresponding to the bank of
+ * the TTBCR being reset.
+ */
+ A32_BANKED_REG_SET(env, c2_base_mask,
+ ((ri->type & ARM_CP_BANK_S) == ARM_CP_BANK_S),
+ 0xffffc000u);
+ A32_BANKED_REG_SET(env, c2_mask,
+ ((ri->type & ARM_CP_BANK_S) == ARM_CP_BANK_S), 0);
raw_write(env, ri, 0);
- env->cp15.c2_mask = 0;
}
static void vmsa_tcr_el1_write(CPUARMState *env, const ARMCPRegInfo *ri,
@@ -4520,7 +4532,7 @@ static bool get_level1_table_address(CPUARMState *env,
uint32_t *table,
* Aarch32 there is a secure and non-secure instance of the translation
* table registers.
*/
- if (address & env->cp15.c2_mask) {
+ if (address & A32_BANKED_CURRENT_REG_GET(env, c2_mask)) {
if (A32_BANKED_CURRENT_REG_GET(env, ttbcr) & TTBCR_PD1) {
/* Translation table walk disabled for TTBR1 */
return false;
@@ -4532,7 +4544,7 @@ static bool get_level1_table_address(CPUARMState *env,
uint32_t *table,
return false;
}
*table = A32_BANKED_CURRENT_REG_GET(env, ttbr0) &
- env->cp15.c2_base_mask;
+ A32_BANKED_CURRENT_REG_GET(env, c2_base_mask);
}
*table |= (address >> 18) & 0x3ffc;
return true;
--
1.8.3.2
- [Qemu-devel] [PATCH v5 13/33] target-arm: move Aarch32 SCR into security reglist, (continued)
- [Qemu-devel] [PATCH v5 13/33] target-arm: move Aarch32 SCR into security reglist, Greg Bellows, 2014/09/30
- [Qemu-devel] [PATCH v5 14/33] target-arm: implement IRQ/FIQ routing to Monitor mode, Greg Bellows, 2014/09/30
- [Qemu-devel] [PATCH v5 16/33] target-arm: add NSACR register, Greg Bellows, 2014/09/30
- [Qemu-devel] [PATCH v5 17/33] target-arm: add SDER definition, Greg Bellows, 2014/09/30
- [Qemu-devel] [PATCH v5 15/33] target-arm: Respect SCR.FW, SCR.AW and SCTLR.NMFI, Greg Bellows, 2014/09/30
- [Qemu-devel] [PATCH v5 20/33] target-arm: make CSSELR banked, Greg Bellows, 2014/09/30
- [Qemu-devel] [PATCH v5 19/33] target-arm: add SCTLR_EL3 and make SCTLR banked, Greg Bellows, 2014/09/30
- [Qemu-devel] [PATCH v5 18/33] target-arm: add MVBAR support, Greg Bellows, 2014/09/30
- [Qemu-devel] [PATCH v5 21/33] target-arm: add TTBR0_EL3 and make TTBR0/1 banked, Greg Bellows, 2014/09/30
- [Qemu-devel] [PATCH v5 24/33] target-arm: make DACR banked, Greg Bellows, 2014/09/30
- [Qemu-devel] [PATCH v5 23/33] target-arm: make c2_mask and c2_base_mask banked,
Greg Bellows <=
- [Qemu-devel] [PATCH v5 27/33] target-arm: make IFAR/DFAR banked, Greg Bellows, 2014/09/30
- [Qemu-devel] [PATCH v5 30/33] target-arm: make MAIR0/1 banked, Greg Bellows, 2014/09/30
- [Qemu-devel] [PATCH v5 28/33] target-arm: make PAR banked, Greg Bellows, 2014/09/30
- [Qemu-devel] [PATCH v5 33/33] target-arm: add cpu feature EL3 to CPUs with Security Extensions, Greg Bellows, 2014/09/30
- [Qemu-devel] [PATCH v5 25/33] target-arm: make IFSR banked, Greg Bellows, 2014/09/30
- [Qemu-devel] [PATCH v5 29/33] target-arm: make VBAR banked, Greg Bellows, 2014/09/30
- [Qemu-devel] [PATCH v5 26/33] target-arm: make DFSR banked, Greg Bellows, 2014/09/30
- [Qemu-devel] [PATCH v5 32/33] target-arm: add GDB scr register, Greg Bellows, 2014/09/30
- [Qemu-devel] [PATCH v5 22/33] target-arm: add TCR_EL3 and make TTBCR banked, Greg Bellows, 2014/09/30