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[Qemu-devel] [PATCH v4 18/21] target-mips: do not allow Status.FR=0 mode
From: |
Leon Alrae |
Subject: |
[Qemu-devel] [PATCH v4 18/21] target-mips: do not allow Status.FR=0 mode in 64-bit FPU |
Date: |
Wed, 8 Oct 2014 11:55:29 +0100 |
Status.FR bit must be ignored on write and read as 1 when an implementation of
Release 6 of the Architecture in which a 64-bit floating point unit is
implemented.
Signed-off-by: Leon Alrae <address@hidden>
Reviewed-by: Yongbok Kim <address@hidden>
---
v3:
* remove line modifying CP0_Status_rw_bitmask as this is done while defining
CPU
---
target-mips/translate.c | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/target-mips/translate.c b/target-mips/translate.c
index 2edd36e..e5ae6b4 100644
--- a/target-mips/translate.c
+++ b/target-mips/translate.c
@@ -17951,6 +17951,12 @@ void cpu_state_reset(CPUMIPSState *env)
}
}
#endif
+ if ((env->insn_flags & ISA_MIPS32R6) &&
+ (env->active_fpu.fcr0 & (1 << FCR0_F64))) {
+ /* Status.FR = 0 mode in 64-bit FPU not allowed in R6 */
+ env->CP0_Status |= (1 << CP0St_FR);
+ }
+
compute_hflags(env);
cs->exception_index = EXCP_NONE;
}
--
2.1.0
- [Qemu-devel] [PATCH v4 09/21] target-mips: redefine Integer Multiply and Divide instructions, (continued)
- [Qemu-devel] [PATCH v4 09/21] target-mips: redefine Integer Multiply and Divide instructions, Leon Alrae, 2014/10/08
- [Qemu-devel] [PATCH v4 11/21] target-mips: Status.UX/SX/KX enable 32-bit address wrapping, Leon Alrae, 2014/10/08
- [Qemu-devel] [PATCH v4 10/21] target-mips: move CLO, DCLO, CLZ, DCLZ, SDBBP and free special2 in R6, Leon Alrae, 2014/10/08
- [Qemu-devel] [PATCH v4 12/21] target-mips: add ALIGN, DALIGN, BITSWAP and DBITSWAP instructions, Leon Alrae, 2014/10/08
- [Qemu-devel] [PATCH v4 13/21] target-mips: add compact and CP1 branches, Leon Alrae, 2014/10/08
- [Qemu-devel] [PATCH v4 14/21] target-mips: add AUI, LSA and PCREL instruction families, Leon Alrae, 2014/10/08
- [Qemu-devel] [PATCH v4 15/21] softfloat: add functions corresponding to IEEE-2008 min/maxNumMag, Leon Alrae, 2014/10/08
- [Qemu-devel] [PATCH v4 17/21] target-mips: add new Floating Point Comparison instructions, Leon Alrae, 2014/10/08
- [Qemu-devel] [PATCH v4 18/21] target-mips: do not allow Status.FR=0 mode in 64-bit FPU,
Leon Alrae <=
- [Qemu-devel] [PATCH v4 19/21] target-mips: remove JR, BLTZAL, BGEZAL and add NAL, BAL instructions, Leon Alrae, 2014/10/08
- [Qemu-devel] [PATCH v4 20/21] mips_malta: update malta's pseudo-bootloader - replace JR with JALR, Leon Alrae, 2014/10/08
- [Qemu-devel] [PATCH v4 16/21] target-mips: add new Floating Point instructions, Leon Alrae, 2014/10/08
- [Qemu-devel] [PATCH v4 21/21] target-mips: define a new generic CPU supporting MIPS64 Release 6 ISA, Leon Alrae, 2014/10/08