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[Qemu-devel] [PULL 22/28] target-mips/translate.c: Update OPC_SYNCI
From: |
Leon Alrae |
Subject: |
[Qemu-devel] [PULL 22/28] target-mips/translate.c: Update OPC_SYNCI |
Date: |
Wed, 15 Oct 2014 10:54:14 +0100 |
From: Dongxue Zhang <address@hidden>
Update OPC_SYNCI with BS_STOP, in order to handle the instructions which saved
in the same TB of the store instruction.
Signed-off-by: Dongxue Zhang <address@hidden>
Reviewed-by: Yongbok Kim <address@hidden>
address@hidden: update microMIPS SYNCI as well]
Signed-off-by: Leon Alrae <address@hidden>
---
target-mips/translate.c | 7 ++++++-
1 file changed, 6 insertions(+), 1 deletion(-)
diff --git a/target-mips/translate.c b/target-mips/translate.c
index 57c2d41..7b9e8cd 100644
--- a/target-mips/translate.c
+++ b/target-mips/translate.c
@@ -13190,6 +13190,9 @@ static void decode_micromips32_opc (CPUMIPSState *env,
DisasContext *ctx,
gen_logic_imm(ctx, OPC_LUI, rs, -1, imm);
break;
case SYNCI:
+ /* Break the TB to be able to sync copied instructions
+ immediately */
+ ctx->bstate = BS_STOP;
break;
case BC2F:
case BC2T:
@@ -16928,7 +16931,9 @@ static void decode_opc (CPUMIPSState *env, DisasContext
*ctx)
break;
case OPC_SYNCI:
check_insn(ctx, ISA_MIPS32R2);
- /* Treat as NOP. */
+ /* Break the TB to be able to sync copied instructions
+ immediately */
+ ctx->bstate = BS_STOP;
break;
case OPC_BPOSGE32: /* MIPS DSP branch */
#if defined(TARGET_MIPS64)
--
2.1.0
- [Qemu-devel] [PULL 15/28] softfloat: add functions corresponding to IEEE-2008 min/maxNumMag, (continued)
- [Qemu-devel] [PULL 15/28] softfloat: add functions corresponding to IEEE-2008 min/maxNumMag, Leon Alrae, 2014/10/15
- [Qemu-devel] [PULL 13/28] target-mips: add compact and CP1 branches, Leon Alrae, 2014/10/15
- [Qemu-devel] [PULL 18/28] target-mips: do not allow Status.FR=0 mode in 64-bit FPU, Leon Alrae, 2014/10/15
- [Qemu-devel] [PULL 17/28] target-mips: add new Floating Point Comparison instructions, Leon Alrae, 2014/10/15
- [Qemu-devel] [PULL 19/28] target-mips: remove JR, BLTZAL, BGEZAL and add NAL, BAL instructions, Leon Alrae, 2014/10/15
- [Qemu-devel] [PULL 14/28] target-mips: add AUI, LSA and PCREL instruction families, Leon Alrae, 2014/10/15
- [Qemu-devel] [PULL 21/28] target-mips: define a new generic CPU supporting MIPS64 Release 6 ISA, Leon Alrae, 2014/10/15
- [Qemu-devel] [PULL 25/28] target-mips/op_helper.c: Remove unused do_lbu() function, Leon Alrae, 2014/10/15
- [Qemu-devel] [PULL 16/28] target-mips: add new Floating Point instructions, Leon Alrae, 2014/10/15
- [Qemu-devel] [PULL 20/28] mips_malta: update malta's pseudo-bootloader - replace JR with JALR, Leon Alrae, 2014/10/15
- [Qemu-devel] [PULL 22/28] target-mips/translate.c: Update OPC_SYNCI,
Leon Alrae <=
- [Qemu-devel] [PULL 26/28] target-mips/translate.c: Add ifdef guard around check_mips64(), Leon Alrae, 2014/10/15
- [Qemu-devel] [PULL 23/28] target-mips: fix broken MIPS16 and microMIPS, Leon Alrae, 2014/10/15
- [Qemu-devel] [PULL 24/28] target-mips/dsp_helper.c: Remove unused function get_DSPControl_24(), Leon Alrae, 2014/10/15
- [Qemu-devel] [PULL 27/28] target-mips/dsp_helper.c: Add ifdef guards around various functions, Leon Alrae, 2014/10/15
- [Qemu-devel] [PULL 28/28] target-mips: Remove unused gen_load_ACX, gen_store_ACX and cpu_ACX, Leon Alrae, 2014/10/15
- Re: [Qemu-devel] [PULL 00/28] target-mips queue, Peter Maydell, 2014/10/16
- Re: [Qemu-devel] [PULL 00/28] target-mips queue, Peter Maydell, 2014/10/22