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[Qemu-devel] [PULL 18/23] target-arm: increase arrays of registers R13 &
From: |
Peter Maydell |
Subject: |
[Qemu-devel] [PULL 18/23] target-arm: increase arrays of registers R13 & R14 |
Date: |
Fri, 24 Oct 2014 12:37:24 +0100 |
From: Fabian Aggeler <address@hidden>
Increasing banked_r13 and banked_r14 to store LR_mon and SP_mon (bank
index 7).
Signed-off-by: Fabian Aggeler <address@hidden>
Signed-off-by: Greg Bellows <address@hidden>
Reviewed-by: Peter Maydell <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>
---
target-arm/cpu.h | 4 ++--
target-arm/machine.c | 4 ++--
2 files changed, 4 insertions(+), 4 deletions(-)
diff --git a/target-arm/cpu.h b/target-arm/cpu.h
index 690686c..e0e3f9b 100644
--- a/target-arm/cpu.h
+++ b/target-arm/cpu.h
@@ -153,8 +153,8 @@ typedef struct CPUARMState {
/* Banked registers. */
uint64_t banked_spsr[8];
- uint32_t banked_r13[6];
- uint32_t banked_r14[6];
+ uint32_t banked_r13[8];
+ uint32_t banked_r14[8];
/* These hold r8-r12. */
uint32_t usr_regs[5];
diff --git a/target-arm/machine.c b/target-arm/machine.c
index 5776ee0..6437690 100644
--- a/target-arm/machine.c
+++ b/target-arm/machine.c
@@ -238,8 +238,8 @@ const VMStateDescription vmstate_arm_cpu = {
},
VMSTATE_UINT32(env.spsr, ARMCPU),
VMSTATE_UINT64_ARRAY(env.banked_spsr, ARMCPU, 8),
- VMSTATE_UINT32_ARRAY(env.banked_r13, ARMCPU, 6),
- VMSTATE_UINT32_ARRAY(env.banked_r14, ARMCPU, 6),
+ VMSTATE_UINT32_ARRAY(env.banked_r13, ARMCPU, 8),
+ VMSTATE_UINT32_ARRAY(env.banked_r14, ARMCPU, 8),
VMSTATE_UINT32_ARRAY(env.usr_regs, ARMCPU, 5),
VMSTATE_UINT32_ARRAY(env.fiq_regs, ARMCPU, 5),
VMSTATE_UINT64_ARRAY(env.elr_el, ARMCPU, 4),
--
1.9.1
- [Qemu-devel] [PULL 16/23] target-arm: Report a valid L1Ip field in CTR_EL0 for CPU type "any", (continued)
- [Qemu-devel] [PULL 16/23] target-arm: Report a valid L1Ip field in CTR_EL0 for CPU type "any", Peter Maydell, 2014/10/24
- [Qemu-devel] [PULL 15/23] target-arm: Correct sense of the DCZID DZP bit, Peter Maydell, 2014/10/24
- [Qemu-devel] [PULL 14/23] arm/virt: enable PSCI emulation support for system emulation, Peter Maydell, 2014/10/24
- [Qemu-devel] [PULL 11/23] target-arm: Handle SMC/HVC undef-if-no-ELx in pre_* helpers, Peter Maydell, 2014/10/24
- [Qemu-devel] [PULL 12/23] target-arm: Add support for A32 and T32 HVC and SMC insns, Peter Maydell, 2014/10/24
- [Qemu-devel] [PULL 08/23] target-arm: add powered off cpu state, Peter Maydell, 2014/10/24
- [Qemu-devel] [PULL 09/23] target-arm: do not set do_interrupt handlers for ARM and AArch64 user modes, Peter Maydell, 2014/10/24
- [Qemu-devel] [PULL 10/23] target-arm: add missing PSCI constants needed for PSCI emulation, Peter Maydell, 2014/10/24
- [Qemu-devel] [PULL 07/23] omap_gpmc.c: Remove duplicate assignment, Peter Maydell, 2014/10/24
- [Qemu-devel] [PULL 17/23] target-arm: correctly UNDEF writes to FPINST/FPINST2 from EL0, Peter Maydell, 2014/10/24
- [Qemu-devel] [PULL 18/23] target-arm: increase arrays of registers R13 & R14,
Peter Maydell <=
- [Qemu-devel] [PULL 20/23] target-arm: reject switching to monitor mode, Peter Maydell, 2014/10/24
- [Qemu-devel] [PULL 13/23] target-arm: add emulation of PSCI calls for system emulation, Peter Maydell, 2014/10/24
- [Qemu-devel] [PULL 05/23] arm_gic: remove unused parameter., Peter Maydell, 2014/10/24
- [Qemu-devel] [PULL 06/23] disas/libvixl/a64/instructions-a64.h: Remove unused constants, Peter Maydell, 2014/10/24
- [Qemu-devel] [PULL 23/23] target-arm: A32: Emulate the SMC instruction, Peter Maydell, 2014/10/24
- [Qemu-devel] [PULL 19/23] target-arm: add arm_is_secure() function, Peter Maydell, 2014/10/24
- [Qemu-devel] [PULL 03/23] hw/arm/boot: register cpu reset handlers if using -bios, Peter Maydell, 2014/10/24
- [Qemu-devel] [PULL 02/23] hw/arm/virt: mark timer in fdt as v8-compatible, Peter Maydell, 2014/10/24
- [Qemu-devel] [PULL 21/23] target-arm: rename arm_current_pl to arm_current_el, Peter Maydell, 2014/10/24
- [Qemu-devel] [PULL 01/23] hmp: Remove "info pcmcia", Peter Maydell, 2014/10/24