Re: [Qemu-devel] Better Cortex-M support?

[Peter Maydell]

On 28 October 2014 13:23, Liviu Ionescu <address@hidden> wrote:
>
> On 28 Oct 2014, at 14:57, Peter Maydell <address@hidden> wrote:
>
>> On 28 October 2014 12:52, Liviu Ionescu <address@hidden> wrote:
>>>
>>> On 28 Oct 2014, at 14:45, Peter Maydell <address@hidden> wrote:
>>>
>>>>> qemu: Unsupported SemiHosting SWI 0x00
>>>>> R00=00000000 R01=00000000 R02=00000000 R03=00000000
>>>>> R04=00000000 R05=00000000 R06=00000000 R07=200ffed8
>>>>> R08=00000000 R09=00000000 R10=00000000 R11=00000000
>>>>> R12=00000000 R13=200ffed8 R14=000022c5 R15=0000157c
>>>>> PSR=60000173 -ZC- T svc32
>>>>> Abort trap: 6
>>>>
>>>> What code sequence and which semihosting function are
>>>> you trying to use here?
>>>
>> ...
>> Can you give the disassembly of the actual code making
>> the semihosting request, please? As you can see we seem
>> to have interpreted this as a semihosting function zero,
>> not 4, but it's hard to see why without seeing what the
>> assembly instructions are that your code is executing.
>
> right, I did some more tests, and the the actual code is:
>
> 00001564 <_ZN3hal7cortexm4diag11SemiHosting4BKPTEiPvS3_>:
>     {
>
>       // 
> ======================================================================
>       int
>       SemiHosting::BKPT(int op, void* p1, void* p2)
>       {
>     1564:       b480            push    {r7}
>     1566:       b085            sub     sp, #20
>     1568:       af00            add     r7, sp, #0
>     156a:       60f8            str     r0, [r7, #12]
>     156c:       60b9            str     r1, [r7, #8]
>     156e:       607a            str     r2, [r7, #4]
>         register int r0 asm("r0");
>         register int r1 asm("r1") __attribute__((unused));
>         register int r2 asm("r2") __attribute__((unused));
>
>         r0 = op;
>     1570:       68f8            ldr     r0, [r7, #12]
>         r1 = (int) p1;
>     1572:       68bb            ldr     r3, [r7, #8]
>     1574:       4619            mov     r1, r3
>         r2 = (int) p2;
>     1576:       687b            ldr     r3, [r7, #4]
>     1578:       461a            mov     r2, r3
>         asm volatile(""
>             " bkpt 0xAB \n"
>             : "=r"(r0)
>             :
>             :
>         );
>     157a:       beab            bkpt    0x00ab
>         return r0;
>     157c:       4603            mov     r3, r0
>       }
>     157e:       4618            mov     r0, r3
>     1580:       3714            adds    r7, #20
>     1582:       46bd            mov     sp, r7
>     1584:       f85d 7b04       ldr.w   r7, [sp], #4
>     1588:       4770            bx      lr
>     158a:       bf00            nop

Hmm. That code looks OK, but as you can see from the register
dump, QEMU thinks that at the point where it complained
r0 is zero.

> I would check the way "bkpt 0x00ab" is processed.

Do you have a test binary (plus qemu command line) you
can send me?

thanks
-- PMM