[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
Re: [Qemu-devel] [PATCH v8 12/27] target-arm: add MVBAR support
From: |
Peter Maydell |
Subject: |
Re: [Qemu-devel] [PATCH v8 12/27] target-arm: add MVBAR support |
Date: |
Fri, 31 Oct 2014 13:35:51 +0000 |
On 30 October 2014 21:28, Greg Bellows <address@hidden> wrote:
> From: Fabian Aggeler <address@hidden>
>
> Use MVBAR register as exception vector base address for
> exceptions taken to CPU monitor mode.
>
> Signed-off-by: Sergey Fedorov <address@hidden>
> Signed-off-by: Fabian Aggeler <address@hidden>
> Signed-off-by: Greg Bellows <address@hidden>
If you put the cp/opc fields in the right order, then
Reviewed-by: Peter Maydell <address@hidden>
(I shan't mention field ordering again but you can assume
it applies to all the other patches in this series too.)
thanks
-- PMM
- [Qemu-devel] [PATCH v8 17/27] target-arm: add TCR_EL3 and make TTBCR banked, (continued)
- [Qemu-devel] [PATCH v8 17/27] target-arm: add TCR_EL3 and make TTBCR banked, Greg Bellows, 2014/10/31
- [Qemu-devel] [PATCH v8 05/27] target-arm: add CPREG secure state support, Greg Bellows, 2014/10/31
- [Qemu-devel] [PATCH v8 01/27] target-arm: extend async excp masking, Greg Bellows, 2014/10/31
- [Qemu-devel] [PATCH v8 04/27] target-arm: add non-secure Translation Block flag, Greg Bellows, 2014/10/31
- [Qemu-devel] [PATCH v8 25/27] target-arm: make c13 cp regs banked (FCSEIDR, ...), Greg Bellows, 2014/10/31
- [Qemu-devel] [PATCH v8 12/27] target-arm: add MVBAR support, Greg Bellows, 2014/10/31
- Re: [Qemu-devel] [PATCH v8 12/27] target-arm: add MVBAR support,
Peter Maydell <=
- [Qemu-devel] [PATCH v8 10/27] target-arm: add NSACR register, Greg Bellows, 2014/10/31
- [Qemu-devel] [PATCH v8 23/27] target-arm: make PAR banked, Greg Bellows, 2014/10/31
- [Qemu-devel] [PATCH v8 20/27] target-arm: make IFSR banked, Greg Bellows, 2014/10/31
- [Qemu-devel] [PATCH v8 11/27] target-arm: add SDER definition, Greg Bellows, 2014/10/31