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Re: [Qemu-devel] [PATCH] mips: Set the CP0.Config3.DSP and CP0.Config3.D
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From: |
Maciej W. Rozycki |
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Subject: |
Re: [Qemu-devel] [PATCH] mips: Set the CP0.Config3.DSP and CP0.Config3.DSP2P bits |
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Date: |
Fri, 7 Nov 2014 17:36:53 +0000 |
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User-agent: |
Alpine 1.10 (DEB 962 2008-03-14) |
On Fri, 7 Nov 2014, Leon Alrae wrote:
> > I have been working with the current trunk, the change applies
> > correctly there AFAICT.
>
> 55a2201 commit added (1 << CP0C3_MSAP) to CP0_Config3 for
> mips32r5-generic which is not present on your patch.
Indeed, my mistake for some reason.
> > I have no objections to changing mips32r5-generic, it is artificial
> > anyway. But what do you mean by DSP and MSA on one CPU having no sense,
> > is there a conflict between the two ASEs?
>
> I was considering making mips32r5-generic less artificial and slowly
> evolve it towards some existing MIPS32R5 CPU, for example P5600 (which
> supports MSA, but doesn't support DSP ASE). Furthermore, none from the
> latest MIPS CPUs supports both ASEs.
Why not leave mips32r5-generic alone then and add a correct entry for
the P5600 instead?
Maciej