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Re: [Qemu-devel] [PATCH v10 07/26] target-arm: insert AArch32 cpregs twi
From: |
Peter Maydell |
Subject: |
Re: [Qemu-devel] [PATCH v10 07/26] target-arm: insert AArch32 cpregs twice into hashtable |
Date: |
Mon, 17 Nov 2014 15:00:34 +0000 |
On 6 November 2014 15:50, Greg Bellows <address@hidden> wrote:
> From: Fabian Aggeler <address@hidden>
>
> Prepare for cp register banking by inserting every cp register twice,
> once for secure world and once for non-secure world.
>
> Signed-off-by: Fabian Aggeler <address@hidden>
> Signed-off-by: Greg Bellows <address@hidden>
> + if (state == ARM_CP_STATE_AA32) {
> + /* Under AArch32 CP registers can be common
> + * (same for secure and non-secure world) or banked.
> + */
> + switch (r->secure) {
> + case ARM_CP_SECSTATE_S:
> + case ARM_CP_SECSTATE_NS:
> + add_cpreg_to_hashtable(cpu, r, opaque, state,
> + r->secure, crm, opc1,
> opc2);
> + break;
Looks like you might have some 3-space indent going on here?
Otherwise
Reviewed-by: Peter Maydell <address@hidden>
thanks
-- PMM
- [Qemu-devel] [PATCH v10 00/26] target-arm: add Security Extensions for CPUs, Greg Bellows, 2014/11/06
- [Qemu-devel] [PATCH v10 01/26] target-arm: extend async excp masking, Greg Bellows, 2014/11/06
- [Qemu-devel] [PATCH v10 03/26] target-arm: add banked register accessors, Greg Bellows, 2014/11/06
- [Qemu-devel] [PATCH v10 02/26] target-arm: add async excp target_el function, Greg Bellows, 2014/11/06
- [Qemu-devel] [PATCH v10 04/26] target-arm: add non-secure Translation Block flag, Greg Bellows, 2014/11/06
- [Qemu-devel] [PATCH v10 05/26] target-arm: add CPREG secure state support, Greg Bellows, 2014/11/06
- [Qemu-devel] [PATCH v10 06/26] target-arm: add secure state bit to CPREG hash, Greg Bellows, 2014/11/06
- [Qemu-devel] [PATCH v10 07/26] target-arm: insert AArch32 cpregs twice into hashtable, Greg Bellows, 2014/11/06
- Re: [Qemu-devel] [PATCH v10 07/26] target-arm: insert AArch32 cpregs twice into hashtable,
Peter Maydell <=
- [Qemu-devel] [PATCH v10 08/26] target-arm: move AArch32 SCR into security reglist, Greg Bellows, 2014/11/06
- [Qemu-devel] [PATCH v10 09/26] target-arm: implement IRQ/FIQ routing to Monitor mode, Greg Bellows, 2014/11/06
- [Qemu-devel] [PATCH v10 10/26] target-arm: add NSACR register, Greg Bellows, 2014/11/06
- [Qemu-devel] [PATCH v10 11/26] target-arm: add SDER definition, Greg Bellows, 2014/11/06
- [Qemu-devel] [PATCH v10 12/26] target-arm: add MVBAR support, Greg Bellows, 2014/11/06
- [Qemu-devel] [PATCH v10 13/26] target-arm: add SCTLR_EL3 and make SCTLR banked, Greg Bellows, 2014/11/06
- [Qemu-devel] [PATCH v10 14/26] target-arm: respect SCR.FW, SCR.AW and SCTLR.NMFI, Greg Bellows, 2014/11/06
- [Qemu-devel] [PATCH v10 15/26] target-arm: make CSSELR banked, Greg Bellows, 2014/11/06