[Qemu-devel] [PATCH] target-mips: Also apply the CP0.Status mask to MTTC0

[Maciej W. Rozycki]

Make CP0.Status writes made with the MTTC0 instruction respect this
register's mask just like all the other places.  Also preserve the
current values of masked out bits.

Signed-off-by: Maciej W. Rozycki <address@hidden>
---
Hi,

 This should be obvious.  Also quite obviously, we are missing a lot of 
stuff in this area so as it is added this is something to watch out for, 
e.g. CP0.ConfigX writes will have to respect the respective masks too.  
But that's another matter.  For the time being, please apply.

  Maciej

qemu-mips-mttc-status.diff
Index: qemu-git-trunk/target-mips/op_helper.c
===================================================================
--- qemu-git-trunk.orig/target-mips/op_helper.c 2014-11-12 07:41:26.597542010 
+0000
+++ qemu-git-trunk/target-mips/op_helper.c      2014-11-12 07:43:02.107518555 
+0000
@@ -1413,9 +1413,10 @@ void helper_mtc0_status(CPUMIPSState *en
 void helper_mttc0_status(CPUMIPSState *env, target_ulong arg1)
 {
     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
+    uint32_t mask = env->CP0_Status_rw_bitmask & ~0xf1000018;
     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
 
-    other->CP0_Status = arg1 & ~0xf1000018;
+    other->CP0_Status = (other->CP0_Status & ~mask) | (arg1 & mask);
     sync_c0_status(env, other, other_tc);
 }