Re: [Qemu-devel] [PATCH] target-mips: Output CP0.Config2-5 in the register dump

[Leon Alrae]

On 18/11/2014 03:20, Maciej W. Rozycki wrote:
> @@ -19276,6 +19276,10 @@ void mips_cpu_dump_state(CPUState *cs, F
>                  env->CP0_Status, env->CP0_Cause, env->CP0_EPC);
>      cpu_fprintf(f, "    Config0 0x%08x Config1 0x%08x LLAddr 0x" 
> TARGET_FMT_lx "\n",
>                  env->CP0_Config0, env->CP0_Config1, env->lladdr);
> +    cpu_fprintf(f, "    Config2 0x%08x Config3 0x%08x\n",
> +                env->CP0_Config2, env->CP0_Config3);
> +    cpu_fprintf(f, "    Config4 0x%08x Config5 0x%08x\n",
> +                env->CP0_Config4, env->CP0_Config5);

Wouldn't it be better to order these registers for example by CP0
Register and Select number rather than putting them at the end? I think
it doesn't matter at the moment as there are just few registers printed
out, but once we start adding more then probably we would like to avoid
having them placed arbitrarily in the output.

Regards,
Leon