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[Qemu-devel] [PATCH v2] target-mips: gdbstub: Clean up FPU register hand
From: |
Maciej W. Rozycki |
Subject: |
[Qemu-devel] [PATCH v2] target-mips: gdbstub: Clean up FPU register handling |
Date: |
Fri, 5 Dec 2014 18:46:04 +0000 |
User-agent: |
Alpine 1.10 (DEB 962 2008-03-14) |
Rewrite the FPU register access parts of `mips_cpu_gdb_read_register'
and `mips_cpu_gdb_write_register' for consistency between each other.
Signed-off-by: Maciej W. Rozycki <address@hidden>
---
Changes from v1:
- missing braces added for blocks required with conditional statements.
qemu-mips-gdbstub-cleanup.diff
Index: qemu-git-trunk/target-mips/gdbstub.c
===================================================================
--- qemu-git-trunk.orig/target-mips/gdbstub.c 2014-12-04 11:55:18.000000000
+0000
+++ qemu-git-trunk/target-mips/gdbstub.c 2014-12-05 18:39:46.348928321
+0000
@@ -29,8 +29,13 @@ int mips_cpu_gdb_read_register(CPUState
if (n < 32) {
return gdb_get_regl(mem_buf, env->active_tc.gpr[n]);
}
- if (env->CP0_Config1 & (1 << CP0C1_FP)) {
- if (n >= 38 && n < 70) {
+ if (env->CP0_Config1 & (1 << CP0C1_FP) && n >= 38 && n < 72) {
+ switch (n) {
+ case 70:
+ return gdb_get_regl(mem_buf, (int32_t)env->active_fpu.fcr31);
+ case 71:
+ return gdb_get_regl(mem_buf, (int32_t)env->active_fpu.fcr0);
+ default:
if (env->CP0_Status & (1 << CP0St_FR)) {
return gdb_get_regl(mem_buf,
env->active_fpu.fpr[n - 38].d);
@@ -39,12 +44,6 @@ int mips_cpu_gdb_read_register(CPUState
env->active_fpu.fpr[n - 38].w[FP_ENDIAN_IDX]);
}
}
- switch (n) {
- case 70:
- return gdb_get_regl(mem_buf, (int32_t)env->active_fpu.fcr31);
- case 71:
- return gdb_get_regl(mem_buf, (int32_t)env->active_fpu.fcr0);
- }
}
switch (n) {
case 32:
@@ -64,8 +63,10 @@ int mips_cpu_gdb_read_register(CPUState
return gdb_get_regl(mem_buf, 0); /* fp */
case 89:
return gdb_get_regl(mem_buf, (int32_t)env->CP0_PRid);
- }
- if (n >= 73 && n <= 88) {
+ default:
+ if (n > 89) {
+ return 0;
+ }
/* 16 embedded regs. */
return gdb_get_regl(mem_buf, 0);
}
@@ -89,15 +90,7 @@ int mips_cpu_gdb_write_register(CPUState
env->active_tc.gpr[n] = tmp;
return sizeof(target_ulong);
}
- if (env->CP0_Config1 & (1 << CP0C1_FP)
- && n >= 38 && n < 72) {
- if (n < 70) {
- if (env->CP0_Status & (1 << CP0St_FR)) {
- env->active_fpu.fpr[n - 38].d = tmp;
- } else {
- env->active_fpu.fpr[n - 38].w[FP_ENDIAN_IDX] = tmp;
- }
- }
+ if (env->CP0_Config1 & (1 << CP0C1_FP) && n >= 38 && n < 72) {
switch (n) {
case 70:
env->active_fpu.fcr31 = tmp & 0xFF83FFFF;
@@ -107,6 +100,13 @@ int mips_cpu_gdb_write_register(CPUState
case 71:
/* FIR is read-only. Ignore writes. */
break;
+ default:
+ if (env->CP0_Status & (1 << CP0St_FR)) {
+ env->active_fpu.fpr[n - 38].d = tmp;
+ } else {
+ env->active_fpu.fpr[n - 38].w[FP_ENDIAN_IDX] = tmp;
+ }
+ break;
}
return sizeof(target_ulong);
}
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