Re: [Qemu-devel] [PATCH 7/8] target-tricore: Fix MFCR/MTCR insn and B fo

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Re: [Qemu-devel] [PATCH 7/8] target-tricore: Fix MFCR/MTCR insn and B fo

From:	Richard Henderson
Subject:	Re: [Qemu-devel] [PATCH 7/8] target-tricore: Fix MFCR/MTCR insn and B format offset.
Date:	Fri, 12 Dec 2014 12:49:56 -0800
User-agent:	Mozilla/5.0 (X11; Linux x86_64; rv:31.0) Gecko/20100101 Thunderbird/31.3.0

On 12/12/2014 09:31 AM, Bastian Koppelmann wrote:
> Fix gen_mtcr using wrong register.
> Fix gen_mtcr/mfcr using sign extended offsets.
> Fix B format insn using not sign extendend offsets.
> 
> Signed-off-by: Bastian Koppelmann <address@hidden>
> ---

Reviewed-by: Richard Henderson <address@hidden>


r~

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[Qemu-devel] [PATCH 0/8] TriCore add instructions of RR and RR1 opcode format, Bastian Koppelmann, 2014/12/12
- [Qemu-devel] [PATCH 4/8] target-tricore: Add instructions of RR opcode format, that have 0x1 as the first opcode, Bastian Koppelmann, 2014/12/12
  - Re: [Qemu-devel] [PATCH 4/8] target-tricore: Add instructions of RR opcode format, that have 0x1 as the first opcode, Richard Henderson, 2014/12/12
- [Qemu-devel] [PATCH 3/8] target-tricore: Add instructions of RR opcode format, that have 0xf as the first opcode, Bastian Koppelmann, 2014/12/12
  - Re: [Qemu-devel] [PATCH 3/8] target-tricore: Add instructions of RR opcode format, that have 0xf as the first opcode, Richard Henderson, 2014/12/12
- [Qemu-devel] [PATCH 5/8] target-tricore: Add instructions of RR opcode format, that have 0x4b as the first opcode, Bastian Koppelmann, 2014/12/12
  - Re: [Qemu-devel] [PATCH 5/8] target-tricore: Add instructions of RR opcode format, that have 0x4b as the first opcode, Richard Henderson, 2014/12/12
    - Re: [Qemu-devel] [PATCH 5/8] target-tricore: Add instructions of RR opcode format, that have 0x4b as the first opcode, Bastian Koppelmann, 2014/12/17
- [Qemu-devel] [PATCH 7/8] target-tricore: Fix MFCR/MTCR insn and B format offset., Bastian Koppelmann, 2014/12/12
  - Re: [Qemu-devel] [PATCH 7/8] target-tricore: Fix MFCR/MTCR insn and B format offset., Richard Henderson <=
- [Qemu-devel] [PATCH 8/8] target-tricore: Add instructions of RR1 opcode format, that have 0xb3 as first opcode, Bastian Koppelmann, 2014/12/12
  - Re: [Qemu-devel] [PATCH 8/8] target-tricore: Add instructions of RR1 opcode format, that have 0xb3 as first opcode, Richard Henderson, 2014/12/12
- [Qemu-devel] [PATCH 1/8] target-tricore: Change SSOV/SUOV makro name to SSOV32/SUOV32, Bastian Koppelmann, 2014/12/12
  - Re: [Qemu-devel] [PATCH 1/8] target-tricore: Change SSOV/SUOV makro name to SSOV32/SUOV32, Richard Henderson, 2014/12/12
- [Qemu-devel] [PATCH 6/8] target-tricore: Add missing 1.6 insn of BOL opcode format, Bastian Koppelmann, 2014/12/12
  - Re: [Qemu-devel] [PATCH 6/8] target-tricore: Add missing 1.6 insn of BOL opcode format, Richard Henderson, 2014/12/12
- [Qemu-devel] [PATCH 2/8] target-tricore: Add instructions of RR opcode format, that have 0xb as the first opcode, Bastian Koppelmann, 2014/12/12
  - Re: [Qemu-devel] [PATCH 2/8] target-tricore: Add instructions of RR opcode format, that have 0xb as the first opcode, Richard Henderson, 2014/12/12

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