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[Qemu-devel] [PULL 11/30] target-mips: Remove unused `FLOAT_OP' macro
From: |
Leon Alrae |
Subject: |
[Qemu-devel] [PULL 11/30] target-mips: Remove unused `FLOAT_OP' macro |
Date: |
Tue, 16 Dec 2014 19:48:57 +0000 |
From: "Maciej W. Rozycki" <address@hidden>
Remove the `FLOAT_OP' macro, unused since commit
b6d96beda3a6cbf20a2d04a609eff78adebd8859 [Use temporary registers for
the MIPS FPU emulation.].
Signed-off-by: Maciej W. Rozycki <address@hidden>
Signed-off-by: Leon Alrae <address@hidden>
---
target-mips/op_helper.c | 2 --
1 file changed, 2 deletions(-)
diff --git a/target-mips/op_helper.c b/target-mips/op_helper.c
index 5a9f207..f547801 100644
--- a/target-mips/op_helper.c
+++ b/target-mips/op_helper.c
@@ -3140,8 +3140,6 @@ uint64_t helper_float_rsqrt1_ps(CPUMIPSState *env,
uint64_t fdt0)
return ((uint64_t)fsth2 << 32) | fst2;
}
-#define FLOAT_OP(name, p) void helper_float_##name##_##p(CPUMIPSState *env)
-
/* binary operations */
#define FLOAT_BINOP(name) \
uint64_t helper_float_ ## name ## _d(CPUMIPSState *env, \
--
2.1.0
- [Qemu-devel] [PULL 00/30] target-mips queue, Leon Alrae, 2014/12/16
- [Qemu-devel] [PULL 01/30] target-mips: Correct the handling of register #72 on writes, Leon Alrae, 2014/12/16
- [Qemu-devel] [PULL 02/30] target-mips: Make CP1.FIR read-only here too, Leon Alrae, 2014/12/16
- [Qemu-devel] [PULL 03/30] target-mips: Add 5KEc and 5KEf MIPS64r2 processors, Leon Alrae, 2014/12/16
- [Qemu-devel] [PULL 09/30] target-mips: Fix formatting in `decode_opc', Leon Alrae, 2014/12/16
- [Qemu-devel] [PULL 10/30] target-mips: Make `helper_float_cvtw_s' consistent with the remaining helpers, Leon Alrae, 2014/12/16
- [Qemu-devel] [PULL 11/30] target-mips: Remove unused `FLOAT_OP' macro,
Leon Alrae <=
- [Qemu-devel] [PULL 13/30] target-mips: Correct MIPS16/microMIPS branch size calculation, Leon Alrae, 2014/12/16
- [Qemu-devel] [PULL 17/30] target-mips: Output CP0.Config2-5 in the register dump, Leon Alrae, 2014/12/16
- [Qemu-devel] [PULL 14/30] target-mips: Correct the handling of writes to CP0.Status for MIPSr6, Leon Alrae, 2014/12/16
- [Qemu-devel] [PULL 15/30] target-mips: Correct the writes to Status and Cause registers via gdbstub, Leon Alrae, 2014/12/16
- [Qemu-devel] [PULL 12/30] target-mips: Restore the order of helpers, Leon Alrae, 2014/12/16
- [Qemu-devel] [PULL 16/30] target-mips: Fix the 64-bit case for microMIPS MOVE16 and MOVEP, Leon Alrae, 2014/12/16
- [Qemu-devel] [PULL 21/30] target-mips: gdbstub: Clean up FPU register handling, Leon Alrae, 2014/12/16
- [Qemu-devel] [PULL 22/30] target-mips: Also apply the CP0.Status mask to MTTC0, Leon Alrae, 2014/12/16
- [Qemu-devel] [PULL 18/30] target-mips: Fix CP0.Config3.ISAOnExc write accesses, Leon Alrae, 2014/12/16
- [Qemu-devel] [PULL 19/30] target-mips: Tighten ISA level checks, Leon Alrae, 2014/12/16