[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
[Qemu-devel] [PULL 05/13] target-tricore: Fix mask handling JNZ.T being
From: |
Bastian Koppelmann |
Subject: |
[Qemu-devel] [PULL 05/13] target-tricore: Fix mask handling JNZ.T being 7 bit long |
Date: |
Sun, 21 Dec 2014 18:47:41 +0000 |
The mask is actually 7 bit long, instead of 6, so the expression checking
for JNZ.T is always false. Let's make the mask 1 bit wider.
Signed-off-by: Bastian Koppelmann <address@hidden>
---
target-tricore/translate.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/target-tricore/translate.c b/target-tricore/translate.c
index 3d87346..8f9e13e 100644
--- a/target-tricore/translate.c
+++ b/target-tricore/translate.c
@@ -3828,8 +3828,8 @@ static void decode_32Bit_opc(CPUTriCoreState *env,
DisasContext *ctx)
op1 = MASK_OP_MAJOR(ctx->opcode);
- /* handle JNZ.T opcode only being 6 bit long */
- if (unlikely((op1 & 0x3f) == OPCM_32_BRN_JTT)) {
+ /* handle JNZ.T opcode only being 7 bit long */
+ if (unlikely((op1 & 0x7f) == OPCM_32_BRN_JTT)) {
op1 = OPCM_32_BRN_JTT;
}
--
2.2.1
- [Qemu-devel] [PULL 00/13] tricore patches, Bastian Koppelmann, 2014/12/21
- [Qemu-devel] [PULL 01/13] target-tricore: fix offset masking in BOL format, Bastian Koppelmann, 2014/12/21
- [Qemu-devel] [PULL 02/13] target-tricore: typo in BOL format, Bastian Koppelmann, 2014/12/21
- [Qemu-devel] [PULL 06/13] target-tricore: Change SSOV/SUOV makro name to SSOV32/SUOV32, Bastian Koppelmann, 2014/12/21
- [Qemu-devel] [PULL 04/13] target-tricore: pretty-print register dump and show more status registers, Bastian Koppelmann, 2014/12/21
- [Qemu-devel] [PULL 11/13] target-tricore: Add missing 1.6 insn of BOL opcode format, Bastian Koppelmann, 2014/12/21
- [Qemu-devel] [PULL 07/13] target-tricore: Add instructions of RR opcode format, that have 0xb as the first opcode, Bastian Koppelmann, 2014/12/21
- [Qemu-devel] [PULL 05/13] target-tricore: Fix mask handling JNZ.T being 7 bit long,
Bastian Koppelmann <=
- [Qemu-devel] [PULL 10/13] target-tricore: Add instructions of RR opcode format, that have 0x4b as the first opcode, Bastian Koppelmann, 2014/12/21
- [Qemu-devel] [PULL 12/13] target-tricore: Fix MFCR/MTCR insn and B format offset., Bastian Koppelmann, 2014/12/21
- [Qemu-devel] [PULL 03/13] target-tricore: add missing 64-bit MOV in RLC format, Bastian Koppelmann, 2014/12/21
- [Qemu-devel] [PULL 08/13] target-tricore: Add instructions of RR opcode format, that have 0xf as the first opcode, Bastian Koppelmann, 2014/12/21
- [Qemu-devel] [PULL 09/13] target-tricore: Add instructions of RR opcode format, that have 0x1 as the first opcode, Bastian Koppelmann, 2014/12/21
- [Qemu-devel] [PULL 13/13] target-tricore: Add instructions of RR1 opcode format, that have 0xb3 as first opcode, Bastian Koppelmann, 2014/12/21
- Re: [Qemu-devel] [PULL 00/13] tricore patches, Peter Maydell, 2014/12/22