Re: [Qemu-devel] [PATCH 4/4] target-arm: Add missing SP_ELx register definition

[Peter Maydell]

On 23 January 2015 at 14:49, Greg Bellows <address@hidden> wrote:
> Added CP register definitions for SP_EL1 and SP_EL2.
>
> Signed-off-by: Greg Bellows <address@hidden>
> ---
>  target-arm/helper.c | 14 ++++++++++++--
>  1 file changed, 12 insertions(+), 2 deletions(-)
>
> diff --git a/target-arm/helper.c b/target-arm/helper.c
> index d5f0997..ae7394d 100644
> --- a/target-arm/helper.c
> +++ b/target-arm/helper.c
> @@ -2096,7 +2096,7 @@ static uint64_t aa64_dczid_read(CPUARMState *env, const 
> ARMCPRegInfo *ri)
>      return cpu->dcz_blocksize | dzp_bit;
>  }
>
> -static CPAccessResult sp_el0_access(CPUARMState *env, const ARMCPRegInfo *ri)
> +static CPAccessResult sp_el_access(CPUARMState *env, const ARMCPRegInfo *ri)

This isn't necessary. The access function for SP_EL0 is there to
check for the "if SPSel.SP is 0 then any access to SP_EL0 using MSR
or MRS is UNDEFINED" case in the spec (ie using MSR/MRS to mess with
the stack pointer currently in use is forbidden). But this isn't
needed for the SP_EL1/2/3, because the RW access permissions ensure
that you can't get at SP_EL1 when you're using it as your SP (and
so the spec for those registers doesn't have any similar clause).
So they can work with just .access and no .accessfn.

>  {
>      if (!(env->pstate & PSTATE_SP)) {
>          /* Access to SP_EL0 is undefined if it's being used as
> @@ -2326,9 +2326,14 @@ static const ARMCPRegInfo v8_cp_reginfo[] = {
>       */
>      { .name = "SP_EL0", .state = ARM_CP_STATE_AA64,
>        .opc0 = 3, .opc1 = 0, .crn = 4, .crm = 1, .opc2 = 0,
> -      .access = PL1_RW, .accessfn = sp_el0_access,
> +      .access = PL1_RW, .accessfn = sp_el_access,
>        .type = ARM_CP_NO_MIGRATE,
>        .fieldoffset = offsetof(CPUARMState, sp_el[0]) },
> +    { .name = "SP_EL1", .state = ARM_CP_STATE_AA64,
> +      .opc0 = 3, .opc1 = 4, .crn = 4, .crm = 1, .opc2 = 0,
> +      .access = PL2_RW, .accessfn = sp_el_access,
> +      .type = ARM_CP_NO_MIGRATE,
> +      .fieldoffset = offsetof(CPUARMState, sp_el[1]) },
>      { .name = "SPSel", .state = ARM_CP_STATE_AA64,
>        .opc0 = 3, .opc1 = 0, .crn = 4, .crm = 2, .opc2 = 0,
>        .type = ARM_CP_NO_MIGRATE,
> @@ -2410,6 +2415,11 @@ static const ARMCPRegInfo v8_el2_cp_reginfo[] = {
>        .access = PL2_RW, .writefn = vbar_write,
>        .fieldoffset = offsetof(CPUARMState, cp15.vbar_el[2]),
>        .resetvalue = 0 },
> +    { .name = "SP_EL2", .state = ARM_CP_STATE_AA64,
> +      .opc0 = 3, .opc1 = 6, .crn = 4, .crm = 1, .opc2 = 0,
> +      .access = PL3_RW, .accessfn = sp_el_access,
> +      .type = ARM_CP_NO_MIGRATE,
> +      .fieldoffset = offsetof(CPUARMState, sp_el[2]) },

Otherwise OK.

thanks
-- PMM