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[Qemu-devel] [PULL v2 08/14] target-mips: Make CP0.Status.CU1 read-only
From: |
Leon Alrae |
Subject: |
[Qemu-devel] [PULL v2 08/14] target-mips: Make CP0.Status.CU1 read-only for the 5Kc and 5KEc processors |
Date: |
Sat, 14 Feb 2015 17:44:58 +0000 |
From: "Maciej W. Rozycki" <address@hidden>
Signed-off-by: Maciej W. Rozycki <address@hidden>
Signed-off-by: Leon Alrae <address@hidden>
---
target-mips/translate_init.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/target-mips/translate_init.c b/target-mips/translate_init.c
index 1543f6c..9e8433a 100644
--- a/target-mips/translate_init.c
+++ b/target-mips/translate_init.c
@@ -474,7 +474,7 @@ static const mips_def_t mips_defs[] =
.CP0_LLAddr_shift = 4,
.SYNCI_Step = 32,
.CCRes = 2,
- .CP0_Status_rw_bitmask = 0x32F8FFFF,
+ .CP0_Status_rw_bitmask = 0x12F8FFFF,
.SEGBITS = 42,
.PABITS = 36,
.insn_flags = CPU_MIPS64,
@@ -575,7 +575,7 @@ static const mips_def_t mips_defs[] =
.CP0_LLAddr_shift = 4,
.SYNCI_Step = 32,
.CCRes = 2,
- .CP0_Status_rw_bitmask = 0x32F8FFFF,
+ .CP0_Status_rw_bitmask = 0x12F8FFFF,
.SEGBITS = 42,
.PABITS = 36,
.insn_flags = CPU_MIPS64R2,
--
2.1.0
- [Qemu-devel] [PULL v2 00/14] target-mips queue, Leon Alrae, 2015/02/14
- [Qemu-devel] [PULL v2 02/14] jazz: do not explode QEMUMachineInitArgs structure, Leon Alrae, 2015/02/14
- [Qemu-devel] [PULL v2 01/14] isa: add memory space parameter to isa_bus_new, Leon Alrae, 2015/02/14
- [Qemu-devel] [PULL v2 09/14] target-mips: fix detection of the end of the page during translation, Leon Alrae, 2015/02/14
- [Qemu-devel] [PULL v2 13/14] target-mips: pass 0 instead of -1 as rs in microMIPS LUI instruction, Leon Alrae, 2015/02/14
- [Qemu-devel] [PULL v2 08/14] target-mips: Make CP0.Status.CU1 read-only for the 5Kc and 5KEc processors,
Leon Alrae <=
- [Qemu-devel] [PULL v2 06/14] gt64xxx: remove isa_mem_base usage, Leon Alrae, 2015/02/14
- [Qemu-devel] [PULL v2 04/14] mips: remove isa_mem_base usage, Leon Alrae, 2015/02/14
- [Qemu-devel] [PULL v2 03/14] jazz: remove usage of isa_mem_base, Leon Alrae, 2015/02/14
- [Qemu-devel] [PULL v2 05/14] piix4: use PCI address space instead of system memory, Leon Alrae, 2015/02/14
- [Qemu-devel] [PULL v2 11/14] target-mips: use CP0EnLo_XI instead of magic number, Leon Alrae, 2015/02/14
- [Qemu-devel] [PULL v2 07/14] isa: remove isa_mem_base variable, Leon Alrae, 2015/02/14
- [Qemu-devel] [PULL v2 14/14] linux-user: correct stat structure in MIPS N32, Leon Alrae, 2015/02/14
- [Qemu-devel] [PULL v2 10/14] target-mips: ll and lld cause AdEL exception for unaligned address, Leon Alrae, 2015/02/14
- [Qemu-devel] [PULL v2 12/14] target-mips: fix broken snapshotting, Leon Alrae, 2015/02/14
- Re: [Qemu-devel] [PULL v2 00/14] target-mips queue, Peter Maydell, 2015/02/17