Re: [Qemu-devel] [PATCH 00/11] target-aarch64 fix and improvments

[Laurent Desnogues]

Hi Richard,

On Thu, Feb 19, 2015 at 10:14 PM, Richard Henderson <address@hidden> wrote:
> While doing the mechanics of a previous patch set converting
> translators to use to TCGLabel pointers, I was reminded of
> several outstanding OPTME comments in the aarch64 translator.
>
> I had started with the csel change, which at first failed and
> took quite some time to debug.  See the comment for patch 1.
>
> Since this depends on the outstanding TCGLabel patch set, the
> full tree is available at
>
>   git://github.com/rth7680/qemu.git arm-movcond

With patch 10 (fccmp) removed and the handling of ALWAYS
and NEVER added to tcg-op.c, I get no failure any more (and
no significant speed change).

Thanks,

Laurent

>
> r~
>
>
> Richard Henderson (11):
>   target-arm: Introduce DisasCompare
>   target-arm: Extend NZCF to 64 bits
>   target-arm: Handle always condition codes within arm_test_cc
>   target-arm: Recognize SXTB, SXTH, SXTW, ASR
>   target-arm: Recognize UXTB, UXTH, LSR, LSL
>   target-arm: Eliminate unnecessary zero-extend in disas_bitfield
>   target-arm: Recognize ROR
>   target-arm: Use setcond and movcond for csel
>   target-arm: Implement ccmp branchless
>   target-arm: Implement fccmp branchless
>   target-arm: Implement fcsel with movcond
>
>  target-arm/cpu.h           |  21 +-
>  target-arm/helper.c        |  18 +-
>  target-arm/translate-a64.c | 688 
> ++++++++++++++++++++++++++-------------------
>  target-arm/translate.c     | 151 ++++++----
>  target-arm/translate.h     |   2 -
>  5 files changed, 524 insertions(+), 356 deletions(-)
>
> --
> 2.1.0
>
>