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[Qemu-devel] [PULL v3 03/26] tpm: Allow 32 & 16 bit accesses to the regi
From: |
Michael S. Tsirkin |
Subject: |
[Qemu-devel] [PULL v3 03/26] tpm: Allow 32 & 16 bit accesses to the registers |
Date: |
Mon, 2 Mar 2015 11:58:28 +0100 |
From: Stefan Berger <address@hidden>
Improve the access to the registers with 32 and 16 bit reads and writes.
Also enable access to a non-base register address, such as reads of the
2nd byte of a register. Map the FIFO byte access to any byte within
its 4 byte register (following specs).
Signed-off-by: Stefan Berger <address@hidden>
Acked-by: Michael S. Tsirkin <address@hidden>
Signed-off-by: Michael S. Tsirkin <address@hidden>
---
hw/tpm/tpm_tis.c | 60 ++++++++++++++++++++++++++++++++++++++++++++------------
1 file changed, 47 insertions(+), 13 deletions(-)
diff --git a/hw/tpm/tpm_tis.c b/hw/tpm/tpm_tis.c
index c0e7cd7..6170693 100644
--- a/hw/tpm/tpm_tis.c
+++ b/hw/tpm/tpm_tis.c
@@ -427,6 +427,7 @@ static uint64_t tpm_tis_mmio_read(void *opaque, hwaddr addr,
uint32_t val = 0xffffffff;
uint8_t locty = tpm_tis_locality_from_addr(addr);
uint32_t avail;
+ uint8_t v;
if (tpm_backend_had_startup_error(s->be_driver)) {
return val;
@@ -476,14 +477,26 @@ static uint64_t tpm_tis_mmio_read(void *opaque, hwaddr
addr,
break;
case TPM_TIS_REG_DATA_FIFO:
if (tis->active_locty == locty) {
- switch (tis->loc[locty].state) {
- case TPM_TIS_STATE_COMPLETION:
- val = tpm_tis_data_read(s, locty);
- break;
- default:
- val = TPM_TIS_NO_DATA_BYTE;
- break;
+ if (size > 4 - (addr & 0x3)) {
+ /* prevent access beyond FIFO */
+ size = 4 - (addr & 0x3);
+ }
+ val = 0;
+ shift = 0;
+ while (size > 0) {
+ switch (tis->loc[locty].state) {
+ case TPM_TIS_STATE_COMPLETION:
+ v = tpm_tis_data_read(s, locty);
+ break;
+ default:
+ v = TPM_TIS_NO_DATA_BYTE;
+ break;
+ }
+ val |= (v << shift);
+ shift += 8;
+ size--;
}
+ shift = 0; /* no more adjustments */
}
break;
case TPM_TIS_REG_DID_VID:
@@ -518,11 +531,13 @@ static void tpm_tis_mmio_write_intern(void *opaque,
hwaddr addr,
{
TPMState *s = opaque;
TPMTISEmuState *tis = &s->s.tis;
- uint16_t off = addr & 0xfff;
+ uint16_t off = addr & 0xffc;
+ uint8_t shift = (addr & 0x3) * 8;
uint8_t locty = tpm_tis_locality_from_addr(addr);
uint8_t active_locty, l;
int c, set_new_locty = 1;
uint16_t len;
+ uint32_t mask = (size == 1) ? 0xff : ((size == 2) ? 0xffff : ~0);
DPRINTF("tpm_tis: write.%u(%08x) = %08x\n", size, (int)addr,
(uint32_t)val);
@@ -535,6 +550,15 @@ static void tpm_tis_mmio_write_intern(void *opaque, hwaddr
addr,
return;
}
+ val &= mask;
+
+ if (shift) {
+ val <<= shift;
+ mask <<= shift;
+ }
+
+ mask ^= 0xffffffff;
+
switch (off) {
case TPM_TIS_REG_ACCESS:
@@ -646,9 +670,10 @@ static void tpm_tis_mmio_write_intern(void *opaque, hwaddr
addr,
break;
}
- tis->loc[locty].inte = (val & (TPM_TIS_INT_ENABLED |
- TPM_TIS_INT_POLARITY_MASK |
- TPM_TIS_INTERRUPTS_SUPPORTED));
+ tis->loc[locty].inte &= mask;
+ tis->loc[locty].inte |= (val & (TPM_TIS_INT_ENABLED |
+ TPM_TIS_INT_POLARITY_MASK |
+ TPM_TIS_INTERRUPTS_SUPPORTED));
break;
case TPM_TIS_REG_INT_VECTOR:
/* hard wired -- ignore */
@@ -747,16 +772,25 @@ static void tpm_tis_mmio_write_intern(void *opaque,
hwaddr addr,
tis->loc[locty].state == TPM_TIS_STATE_COMPLETION) {
/* drop the byte */
} else {
- DPRINTF("tpm_tis: Byte to send to TPM: %02x\n", (uint8_t)val);
+ DPRINTF("tpm_tis: Data to send to TPM: %08x (size=%d)\n",
+ val, size);
if (tis->loc[locty].state == TPM_TIS_STATE_READY) {
tis->loc[locty].state = TPM_TIS_STATE_RECEPTION;
tis->loc[locty].sts = TPM_TIS_STS_EXPECT | TPM_TIS_STS_VALID;
}
- if ((tis->loc[locty].sts & TPM_TIS_STS_EXPECT)) {
+ val >>= shift;
+ if (size > 4 - (addr & 0x3)) {
+ /* prevent access beyond FIFO */
+ size = 4 - (addr & 0x3);
+ }
+
+ while ((tis->loc[locty].sts & TPM_TIS_STS_EXPECT) && size > 0) {
if (tis->loc[locty].w_offset < tis->loc[locty].w_buffer.size) {
tis->loc[locty].w_buffer.
buffer[tis->loc[locty].w_offset++] = (uint8_t)val;
+ val >>= 8;
+ size--;
} else {
tis->loc[locty].sts = TPM_TIS_STS_VALID;
}
--
MST
- [Qemu-devel] [PULL v3 00/26] pci, pc, virtio fixes and cleanups, Michael S. Tsirkin, 2015/03/02
- [Qemu-devel] [PULL v3 01/26] balloon: call qdev_alias_all_properties for proxy dev in balloon class init, Michael S. Tsirkin, 2015/03/02
- [Qemu-devel] [PULL v3 02/26] tpm: Extend sts register to 32 bit, Michael S. Tsirkin, 2015/03/02
- [Qemu-devel] [PULL v3 04/26] tpm: Support for XFIFO register, Michael S. Tsirkin, 2015/03/02
- [Qemu-devel] [PULL v3 03/26] tpm: Allow 32 & 16 bit accesses to the registers,
Michael S. Tsirkin <=
- [Qemu-devel] [PULL v3 05/26] tpm: Support for TIS selftest done flag, Michael S. Tsirkin, 2015/03/02
- [Qemu-devel] [PULL v3 06/26] tpm: Support for capability flags of TIS 1.3, Michael S. Tsirkin, 2015/03/02
- [Qemu-devel] [PULL v3 09/26] pc: acpi: drop manual hole punching for CPU hotplug resources, Michael S. Tsirkin, 2015/03/02
- [Qemu-devel] [PULL v3 07/26] pc: acpi-build: create PCI0._CRS dynamically, Michael S. Tsirkin, 2015/03/02
- [Qemu-devel] [PULL v3 08/26] pc: acpi: drop manual hole punching for PCI hotplug resources, Michael S. Tsirkin, 2015/03/02
- [Qemu-devel] [PULL v3 10/26] pc: acpi: drop manual hole punching for GPE0 resources, Michael S. Tsirkin, 2015/03/02
- [Qemu-devel] [PULL v3 12/26] acpi: add acpi_irq_no_flags() term, Michael S. Tsirkin, 2015/03/02
- [Qemu-devel] [PULL v3 11/26] pc: acpi-build: drop remaining ssdt_misc template, Michael S. Tsirkin, 2015/03/02
- [Qemu-devel] [PULL v3 13/26] pc: export applesmc IO port/len, Michael S. Tsirkin, 2015/03/02
- [Qemu-devel] [PULL v3 14/26] pc: acpi-build: drop template patching and create Device(SMC) dynamically, Michael S. Tsirkin, 2015/03/02