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[Qemu-devel] [PULL 2/6] target-tricore: fix msub32_suov return wrong res
From: |
Bastian Koppelmann |
Subject: |
[Qemu-devel] [PULL 2/6] target-tricore: fix msub32_suov return wrong results |
Date: |
Tue, 3 Mar 2015 01:18:21 +0000 |
If the signed result of the multiplication overflows, we would get a negative
value, which would result in a addition instead of a subtraction.
Now we do the overflow calculation and saturation by hand instead of using
suov32_neg.
Signed-off-by: Bastian Koppelmann <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
---
target-tricore/op_helper.c | 27 +++++++++++++++++++++------
1 file changed, 21 insertions(+), 6 deletions(-)
diff --git a/target-tricore/op_helper.c b/target-tricore/op_helper.c
index ed26b30..08bf4ae 100644
--- a/target-tricore/op_helper.c
+++ b/target-tricore/op_helper.c
@@ -443,13 +443,28 @@ target_ulong helper_msub32_ssov(CPUTriCoreState *env,
target_ulong r1,
target_ulong helper_msub32_suov(CPUTriCoreState *env, target_ulong r1,
target_ulong r2, target_ulong r3)
{
- int64_t t1 = extract64(r1, 0, 32);
- int64_t t2 = extract64(r2, 0, 32);
- int64_t t3 = extract64(r3, 0, 32);
- int64_t result;
+ uint64_t t1 = extract64(r1, 0, 32);
+ uint64_t t2 = extract64(r2, 0, 32);
+ uint64_t t3 = extract64(r3, 0, 32);
+ uint64_t result;
+ uint64_t mul;
- result = t2 - (t1 * t3);
- return suov32_neg(env, result);
+ mul = (t1 * t3);
+ result = t2 - mul;
+
+ env->PSW_USB_AV = result ^ result * 2u;
+ env->PSW_USB_SAV |= env->PSW_USB_AV;
+ /* we calculate ovf by hand here, because the multiplication can overflow
on
+ the host, which would give false results if we compare to less than
+ zero */
+ if (mul > t2) {
+ env->PSW_USB_V = (1 << 31);
+ env->PSW_USB_SV = (1 << 31);
+ result = 0;
+ } else {
+ env->PSW_USB_V = 0;
+ }
+ return result;
}
uint64_t helper_msub64_ssov(CPUTriCoreState *env, target_ulong r1,
--
2.3.1
- [Qemu-devel] [PULL 0/6] tricore patches for 2.3, Bastian Koppelmann, 2015/03/02
- [Qemu-devel] [PULL 4/6] target-tricore: Add instructions of RRR1 opcode format, which have 0x83 as first opcode, Bastian Koppelmann, 2015/03/02
- [Qemu-devel] [PULL 6/6] target-tricore: Add instructions of RRR1 opcode format, which have 0xc3 as first opcode, Bastian Koppelmann, 2015/03/02
- [Qemu-devel] [PULL 5/6] target-tricore: Add instructions of RRR1 opcode format, which have 0x43 as first opcode, Bastian Koppelmann, 2015/03/02
- [Qemu-devel] [PULL 3/6] target-tricore: Add instructions of RRR2 opcode format, Bastian Koppelmann, 2015/03/02
- [Qemu-devel] [PULL 2/6] target-tricore: fix msub32_suov return wrong results,
Bastian Koppelmann <=
- [Qemu-devel] [PULL 1/6] target-tricore: Fix RLC_ADDI, RLC_ADDIH using wrong microcode helper, Bastian Koppelmann, 2015/03/02
- Re: [Qemu-devel] [PULL 0/6] tricore patches for 2.3, Peter Maydell, 2015/03/08
- [Qemu-devel] [PULL 0/6] tricore patches for 2.3, Bastian Koppelmann, 2015/03/16
- [Qemu-devel] [PULL 2/6] target-tricore: Add instructions of RRR1 opcode format, which have 0x63 as first opcode, Bastian Koppelmann, 2015/03/16
- [Qemu-devel] [PULL 6/6] target-tricore: Add instructions of SYS opcode format, Bastian Koppelmann, 2015/03/16
- [Qemu-devel] [PULL 3/6] target-tricore: Add instructions of RRR1 opcode format, which have 0xe3 as first opcode, Bastian Koppelmann, 2015/03/16
- [Qemu-devel] [PULL 5/6] target-tricore: Add instructions of RRRW opcode format, Bastian Koppelmann, 2015/03/16
- [Qemu-devel] [PULL 4/6] target-tricore: Add instructions of RRRR opcode format, Bastian Koppelmann, 2015/03/16
- [Qemu-devel] [PULL 1/6] target-tricore: Add instructions of RRR1 opcode format, which have 0xa3 as first opcode, Bastian Koppelmann, 2015/03/16
- Re: [Qemu-devel] [PULL 0/6] tricore patches for 2.3, Peter Maydell, 2015/03/16