[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
[Qemu-devel] [PATCH v4 5/5] target-arm: cpu.h document why env->spsr exi
From: |
Alex Bennée |
Subject: |
[Qemu-devel] [PATCH v4 5/5] target-arm: cpu.h document why env->spsr exists |
Date: |
Mon, 16 Mar 2015 11:01:56 +0000 |
I was getting very confused about the duplication of state so wanted to
make it explicit.
Signed-off-by: Alex Bennée <address@hidden>
diff --git a/target-arm/cpu.h b/target-arm/cpu.h
index 083211c..6dc1799 100644
--- a/target-arm/cpu.h
+++ b/target-arm/cpu.h
@@ -155,6 +155,11 @@ typedef struct CPUARMState {
This contains all the other bits. Use cpsr_{read,write} to access
the whole CPSR. */
uint32_t uncached_cpsr;
+ /* The spsr is a alias for spsr_elN where N is the current
+ * exception level. It is provided for here so the TCG msr/mrs
+ * implementation can access one register. Care needs to be taken
+ * to ensure the banked_spsr[] is also updated.
+ */
uint32_t spsr;
/* Banked registers. */
--
2.3.2