Re: [Qemu-devel] [PATCH v2] target-arm: Store SPSR_EL1 state in banked_spsr[1] (SPSR_svc)

[Peter Maydell]

On 17 March 2015 at 19:38, Christoffer Dall <address@hidden> wrote:
> On Tue, Mar 17, 2015 at 07:32:15PM +0000, Peter Maydell wrote:
>> The AArch64 SPSR_EL1 register is architecturally mandated to
>> be mapped to the AArch32 SPSR_svc register. This means its
>> state should live in QEMU's env->banked_spsr[1] field.
>> Correct the various places in the code that incorrectly
>> put it in banked_spsr[0].
>>
>> Signed-off-by: Peter Maydell <address@hidden>
>
> Reviewed-by: Christoffer Dall <address@hidden>

Thanks. It also occurs to me that we could avoid some of these
magic 1/6/7 numbers by defining some constants BANK_USR,
BANK_SVC, BANK_ABT, etc for the return values from bank_number
(ie the indexes into env->banked_* arrays),
and then using them where we need to refer to particular
banked_* entries elsewhere. Then for instance this array
in aarch64_banked_spsr_index() looks like

         [1] = BANK_SVC, /* EL1.  */
         [2] = BANK_HYP, /* EL2.  */
         [3] = BANK_MON, /* EL3.  */

and the mapping between the AArch32 and AArch64 SPSRs is
suddenly much more obvious and easy to check.

-- PMM