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Re: [Qemu-devel] [PATCH v5 3/6] hw/intc: arm_gic_kvm.c restore config fi
From: |
Peter Maydell |
Subject: |
Re: [Qemu-devel] [PATCH v5 3/6] hw/intc: arm_gic_kvm.c restore config first |
Date: |
Thu, 26 Mar 2015 17:12:48 +0000 |
On 23 March 2015 at 17:05, Alex Bennée <address@hidden> wrote:
> As there is logic to deal with the difference between edge and level
> triggered interrupts in the kernel we must ensure it knows the
> configuration of the IRQs before we restore the pending state.
>
> Signed-off-by: Alex Bennée <address@hidden>
> Acked-by: Christoffer Dall <address@hidden>
>
> diff --git a/hw/intc/arm_gic_kvm.c b/hw/intc/arm_gic_kvm.c
> index 0d20750..e2512f1 100644
> --- a/hw/intc/arm_gic_kvm.c
> +++ b/hw/intc/arm_gic_kvm.c
> @@ -370,6 +370,11 @@ static void kvm_arm_gic_put(GICState *s)
> * the appropriate CPU interfaces in the kernel) */
> kvm_dist_put(s, 0x800, 8, s->num_irq, translate_targets);
>
> + /* irq_state[n].trigger -> GICD_ICFGRn
> + * (restore targets before pending IRQs so we treat level/edge
> + * correctly */
> + kvm_dist_put(s, 0xc00, 2, s->num_irq, translate_trigger);
You don't seem to have acted on Christoffer's query in v4
about this comment...
-- PMM
- [Qemu-devel] [PATCH v5 1/6] target-arm: Store SPSR_EL1 state in banked_spsr[1] (SPSR_svc), (continued)
- [Qemu-devel] [PATCH v5 1/6] target-arm: Store SPSR_EL1 state in banked_spsr[1] (SPSR_svc), Alex Bennée, 2015/03/23
- [Qemu-devel] [PATCH v5 4/6] target-arm: kvm64 sync FP register state, Alex Bennée, 2015/03/23
- [Qemu-devel] [PATCH v5 5/6] target-arm: kvm64 fix save/restore of SPSR regs, Alex Bennée, 2015/03/23
- [Qemu-devel] [PATCH v5 2/6] target-arm: kvm: save/restore mp state, Alex Bennée, 2015/03/23
- [Qemu-devel] [PATCH v5 3/6] hw/intc: arm_gic_kvm.c restore config first, Alex Bennée, 2015/03/23
- Re: [Qemu-devel] [PATCH v5 3/6] hw/intc: arm_gic_kvm.c restore config first,
Peter Maydell <=