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[Qemu-devel] [PULL 4/8] target-arm: Store SPSR_EL1 state in banked_spsr[
From: |
Peter Maydell |
Subject: |
[Qemu-devel] [PULL 4/8] target-arm: Store SPSR_EL1 state in banked_spsr[1] (SPSR_svc) |
Date: |
Wed, 1 Apr 2015 18:08:14 +0100 |
The AArch64 SPSR_EL1 register is architecturally mandated to
be mapped to the AArch32 SPSR_svc register. This means its
state should live in QEMU's env->banked_spsr[1] field.
Correct the various places in the code that incorrectly
put it in banked_spsr[0].
Signed-off-by: Peter Maydell <address@hidden>
---
target-arm/helper-a64.c | 2 +-
target-arm/helper.c | 2 +-
target-arm/internals.h | 5 ++++-
3 files changed, 6 insertions(+), 3 deletions(-)
diff --git a/target-arm/helper-a64.c b/target-arm/helper-a64.c
index 7e0d038..861f6fa 100644
--- a/target-arm/helper-a64.c
+++ b/target-arm/helper-a64.c
@@ -523,7 +523,7 @@ void aarch64_cpu_do_interrupt(CPUState *cs)
aarch64_save_sp(env, arm_current_el(env));
env->elr_el[new_el] = env->pc;
} else {
- env->banked_spsr[0] = cpsr_read(env);
+ env->banked_spsr[aarch64_banked_spsr_index(new_el)] = cpsr_read(env);
if (!env->thumb) {
env->cp15.esr_el[new_el] |= 1 << 25;
}
diff --git a/target-arm/helper.c b/target-arm/helper.c
index 10886c5..d77c6de 100644
--- a/target-arm/helper.c
+++ b/target-arm/helper.c
@@ -2438,7 +2438,7 @@ static const ARMCPRegInfo v8_cp_reginfo[] = {
{ .name = "SPSR_EL1", .state = ARM_CP_STATE_AA64,
.type = ARM_CP_ALIAS,
.opc0 = 3, .opc1 = 0, .crn = 4, .crm = 0, .opc2 = 0,
- .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, banked_spsr[0]) },
+ .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, banked_spsr[1]) },
/* We rely on the access checks not allowing the guest to write to the
* state field when SPSel indicates that it's being used as the stack
* pointer.
diff --git a/target-arm/internals.h b/target-arm/internals.h
index bb171a7..2cc3017 100644
--- a/target-arm/internals.h
+++ b/target-arm/internals.h
@@ -82,11 +82,14 @@ static inline void arm_log_exception(int idx)
/*
* For AArch64, map a given EL to an index in the banked_spsr array.
+ * Note that this mapping and the AArch32 mapping defined in bank_number()
+ * must agree such that the AArch64<->AArch32 SPSRs have the architecturally
+ * mandated mapping between each other.
*/
static inline unsigned int aarch64_banked_spsr_index(unsigned int el)
{
static const unsigned int map[4] = {
- [1] = 0, /* EL1. */
+ [1] = 1, /* EL1. */
[2] = 6, /* EL2. */
[3] = 7, /* EL3. */
};
--
1.9.1
- [Qemu-devel] [PULL 0/8] target-arm queue, Peter Maydell, 2015/04/01
- [Qemu-devel] [PULL 2/8] hw/arm/vexpress: Fix memory leak reported by Coverity, Peter Maydell, 2015/04/01
- [Qemu-devel] [PULL 8/8] target-arm: kvm64 fix save/restore of SPSR regs, Peter Maydell, 2015/04/01
- [Qemu-devel] [PULL 6/8] hw/intc: arm_gic_kvm.c restore config first, Peter Maydell, 2015/04/01
- [Qemu-devel] [PULL 7/8] target-arm: kvm64 sync FP register state, Peter Maydell, 2015/04/01
- [Qemu-devel] [PULL 4/8] target-arm: Store SPSR_EL1 state in banked_spsr[1] (SPSR_svc),
Peter Maydell <=
- [Qemu-devel] [PULL 3/8] hw/arm/virt: Fix memory leak reported by Coverity, Peter Maydell, 2015/04/01
- [Qemu-devel] [PULL 5/8] target-arm: kvm: save/restore mp state, Peter Maydell, 2015/04/01
- [Qemu-devel] [PULL 1/8] hw/arm/highbank: Fix resource leak and wrong image loading, Peter Maydell, 2015/04/01
- Re: [Qemu-devel] [PULL 0/8] target-arm queue, Peter Maydell, 2015/04/01