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Re: [Qemu-devel] [PATCH target-arm v6 00/14] Next Generation Xilinx Zynq

From: Peter Maydell
Subject: Re: [Qemu-devel] [PATCH target-arm v6 00/14] Next Generation Xilinx Zynq SoC
Date: Wed, 6 May 2015 14:26:54 +0100

On 6 May 2015 at 14:21, Peter Crosthwaite <address@hidden> wrote:
> On Wed, May 6, 2015 at 6:18 AM, Peter Maydell <address@hidden> wrote:
>> On 6 May 2015 at 14:02, Peter Crosthwaite <address@hidden> wrote:
>>> Actually NVM. I got it working on a diff machine. Did you have any
>>> thoughts on the GICC mirror issue while I respin?
>> You mean the thing where the GICC might not be at the bottom of
>> a 64K page? Just map it wherever it lives in the hardware you're
>> modelling... If your h/w is one of the few that's taken the
>> "map the pages mirrored over the page" then a suitable container
>> and aliases should handle that I think.
> Ok, should the alias be machine model level or an option for gic itself?

It's not really part of the GIC, it's a machine model wiring thing.
(This is only relevant if you have an external GIC that's not part
of the CPU proper anyway.)

-- PMM

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