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[Qemu-devel] [PULL 15/19] hw/intc/arm_gic: Change behavior of IAR writes
From: |
Peter Maydell |
Subject: |
[Qemu-devel] [PULL 15/19] hw/intc/arm_gic: Change behavior of IAR writes |
Date: |
Mon, 11 May 2015 14:40:34 +0100 |
From: Fabian Aggeler <address@hidden>
Grouping (GICv2) and Security Extensions change the behavior of IAR
reads. Acknowledging Group0 interrupts is only allowed from Secure
state and acknowledging Group1 interrupts from Secure state is only
allowed if AckCtl bit is set.
Signed-off-by: Fabian Aggeler <address@hidden>
Signed-off-by: Greg Bellows <address@hidden>
Reviewed-by: Edgar E. Iglesias <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>
Message-id: address@hidden
Message-id: address@hidden
[PMM: simplify significantly by reusing the existing
gic_get_current_pending_irq() rather than reimplementing the
same logic here]
Signed-off-by: Peter Maydell <address@hidden>
---
hw/intc/arm_gic.c | 22 ++++++++++++++++------
hw/intc/armv7m_nvic.c | 2 +-
hw/intc/gic_internal.h | 2 +-
3 files changed, 18 insertions(+), 8 deletions(-)
diff --git a/hw/intc/arm_gic.c b/hw/intc/arm_gic.c
index 4ad80e7..6abdb14 100644
--- a/hw/intc/arm_gic.c
+++ b/hw/intc/arm_gic.c
@@ -213,14 +213,24 @@ static void gic_set_running_irq(GICState *s, int cpu, int
irq)
gic_update(s);
}
-uint32_t gic_acknowledge_irq(GICState *s, int cpu)
+uint32_t gic_acknowledge_irq(GICState *s, int cpu, MemTxAttrs attrs)
{
int ret, irq, src;
int cm = 1 << cpu;
- irq = s->current_pending[cpu];
- if (irq == 1023
- || GIC_GET_PRIORITY(irq, cpu) >= s->running_priority[cpu]) {
- DPRINTF("ACK no pending IRQ\n");
+
+ /* gic_get_current_pending_irq() will return 1022 or 1023 appropriately
+ * for the case where this GIC supports grouping and the pending interrupt
+ * is in the wrong group.
+ */
+ irq = gic_get_current_pending_irq(s, cpu, attrs);;
+
+ if (irq >= GIC_MAXIRQ) {
+ DPRINTF("ACK, no pending interrupt or it is hidden: %d\n", irq);
+ return irq;
+ }
+
+ if (GIC_GET_PRIORITY(irq, cpu) >= s->running_priority[cpu]) {
+ DPRINTF("ACK, pending interrupt (%d) has insufficient priority\n",
irq);
return 1023;
}
s->last_active[irq][cpu] = s->running_irq[cpu];
@@ -920,7 +930,7 @@ static MemTxResult gic_cpu_read(GICState *s, int cpu, int
offset,
}
break;
case 0x0c: /* Acknowledge */
- *data = gic_acknowledge_irq(s, cpu);
+ *data = gic_acknowledge_irq(s, cpu, attrs);
break;
case 0x14: /* Running Priority */
*data = gic_get_running_priority(s, cpu, attrs);
diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c
index 1bfff75..e13b729 100644
--- a/hw/intc/armv7m_nvic.c
+++ b/hw/intc/armv7m_nvic.c
@@ -131,7 +131,7 @@ int armv7m_nvic_acknowledge_irq(void *opaque)
nvic_state *s = (nvic_state *)opaque;
uint32_t irq;
- irq = gic_acknowledge_irq(&s->gic, 0);
+ irq = gic_acknowledge_irq(&s->gic, 0, MEMTXATTRS_UNSPECIFIED);
if (irq == 1023)
hw_error("Interrupt but no vector\n");
if (irq >= 32)
diff --git a/hw/intc/gic_internal.h b/hw/intc/gic_internal.h
index d3cebef..20c1e8a 100644
--- a/hw/intc/gic_internal.h
+++ b/hw/intc/gic_internal.h
@@ -78,7 +78,7 @@
#define REV_NVIC 0xffffffff
void gic_set_pending_private(GICState *s, int cpu, int irq);
-uint32_t gic_acknowledge_irq(GICState *s, int cpu);
+uint32_t gic_acknowledge_irq(GICState *s, int cpu, MemTxAttrs attrs);
void gic_complete_irq(GICState *s, int cpu, int irq, MemTxAttrs attrs);
void gic_update(GICState *s);
void gic_init_irqs_and_distributor(GICState *s);
--
1.9.1
- [Qemu-devel] [PULL 03/19] hw/intc/arm_gic: Create outbound FIQ lines, (continued)
- [Qemu-devel] [PULL 03/19] hw/intc/arm_gic: Create outbound FIQ lines, Peter Maydell, 2015/05/11
- [Qemu-devel] [PULL 09/19] hw/intc/arm_gic: Make ICCBPR/GICC_BPR banked, Peter Maydell, 2015/05/11
- [Qemu-devel] [PULL 06/19] hw/intc/arm_gic: Add Interrupt Group Registers, Peter Maydell, 2015/05/11
- [Qemu-devel] [PULL 04/19] hw/intc/arm_gic: Add Security Extensions property, Peter Maydell, 2015/05/11
- [Qemu-devel] [PULL 08/19] hw/intc/arm_gic: Make ICDDCR/GICD_CTLR banked, Peter Maydell, 2015/05/11
- [Qemu-devel] [PULL 19/19] hw/arm/highbank.c: Wire FIQ between CPU <> GIC, Peter Maydell, 2015/05/11
- [Qemu-devel] [PULL 10/19] hw/intc/arm_gic: Make ICCICR/GICC_CTLR banked, Peter Maydell, 2015/05/11
- [Qemu-devel] [PULL 17/19] hw/arm/virt.c: Wire FIQ between CPU <> GIC, Peter Maydell, 2015/05/11
- [Qemu-devel] [PULL 16/19] hw/intc/arm_gic: Add grouping support to gic_update(), Peter Maydell, 2015/05/11
- [Qemu-devel] [PULL 11/19] hw/intc/arm_gic: Implement Non-secure view of RPR, Peter Maydell, 2015/05/11
- [Qemu-devel] [PULL 15/19] hw/intc/arm_gic: Change behavior of IAR writes,
Peter Maydell <=
- [Qemu-devel] [PULL 07/19] hw/intc/arm_gic_kvm.c: Save and restore GICD_IGROUPRn state, Peter Maydell, 2015/05/11
- [Qemu-devel] [PULL 14/19] hw/intc/arm_gic: Change behavior of EOIR writes, Peter Maydell, 2015/05/11
- [Qemu-devel] [PULL 01/19] armv7m_nvic: systick: Reload the RELOAD value and count down only if ENABLE bit is set, Peter Maydell, 2015/05/11
- [Qemu-devel] [PULL 13/19] hw/intc/arm_gic: Handle grouping for GICC_HPPIR, Peter Maydell, 2015/05/11
- [Qemu-devel] [PULL 18/19] hw/arm/vexpress.c: Wire FIQ between CPU <> GIC, Peter Maydell, 2015/05/11
- [Qemu-devel] [PULL 02/19] hw/sd: Don't pass BlockBackend to sd_reset(), Peter Maydell, 2015/05/11
- [Qemu-devel] [PULL 12/19] hw/intc/arm_gic: Restrict priority view, Peter Maydell, 2015/05/11
- [Qemu-devel] [PULL 05/19] hw/intc/arm_gic: Switch to read/write callbacks with tx attributes, Peter Maydell, 2015/05/11
- Re: [Qemu-devel] [PULL 00/19] target-arm queue, Peter Maydell, 2015/05/12