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Re: [Qemu-devel] Supporting multiple CPU AddressSpaces and memory transa
Re: [Qemu-devel] Supporting multiple CPU AddressSpaces and memory transaction attributes
Wed, 13 May 2015 11:28:38 +0200
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On 13/05/2015 08:41, Edgar E. Iglesias wrote:
> I think it would be nice if address_space_translate_for_iotlb
> was allowed to modify the attributes so that an IOMMU in front
> of a CPU could for example down-grade a secure to a non-secure accesse
> (once we add IOMMU support in front of CPUs). If I understood correctly
> the memattrs would stay as a separate field in the iotlb, so this
> would be easy to implement?
Yes, it should.
> The naive implementation I have keeps pointers to AS and the memattrs
> in the iotlb. address_space_translate_for_iotlb walks any IOMMU
> translate() fns, if it hits a RAM it returns the host addr as usual.
How is the TLB invalidated on IOMMU changes?
> If it hits MMIO behind IOMMUs it returns the first memsection, i.e
> the one pointing to the iommu-ops and lets the IO access helpers
> deal with the access via address_space_rw (for every IO access, slow).