On 23 May 2015 at 13:18, 浩倫 魏 <address@hidden
> Hi, all:
> I've been trying to understand the process of binary translation inside TCG.
> If I haven't misunderstood, qemu_ld/st are the operations that will call
> helper function(ld_mmu) to let softmmu translate the GVA->GPA for the guest
> load/store instructions.
> So there are some points that I hope you can help me out:
> 1. Is every guest load/store instruction would be translated to qemu_ld/st
Yes, as a general rule. There are a few special cases:
* sometimes complicated instructions are just translated into
calls to helper functions which do the guest memory access
at runtime (for instance x86 cmpxchg8b turns into a call to
* for linux-user some of the atomic instructions (load-lock/
store-conditional pairs) are handled by translating to a
"raise internal exception" call, and the actual load/store
is then dealt with in linux-user/main.c
[This mechanism might change in the near future; we're looking at
multi-threaded TCG emulation, and so might switch the linux-user
atomics to work the same way as a future mechanism for doing atomics
in multi-threaded system emulation]
But almost all guest accesses will turn into qemu_ld/st ops.
> 2. What about another TCG IR "ld/st"? What kind of guest instructions would
> cause TCG generates that IRs and for what purpose?
These just do plain load/store to the *host* address specified.
This is almost always used to read a value from the CPU state
structure (CPUARMState, etc). Generated code always has access
to a pointer to this struct, and uses the ld/st ops to read
or write fields within it. (If you search for tcg_gen_ld
in target-*/ you'll see lots of examples.) The op can be used
for any host load or store, but in practice use for anything
other than "read a value from the CPU state struct" is very rare.