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[Qemu-devel] [PATCH v2 11/14] target-arm: Add CNTHCTL_EL2
From: |
Edgar E. Iglesias |
Subject: |
[Qemu-devel] [PATCH v2 11/14] target-arm: Add CNTHCTL_EL2 |
Date: |
Wed, 27 May 2015 17:27:36 +1000 |
From: "Edgar E. Iglesias" <address@hidden>
Signed-off-by: Edgar E. Iglesias <address@hidden>
---
target-arm/cpu.h | 1 +
target-arm/helper.c | 32 ++++++++++++++++++++++++++++++--
2 files changed, 31 insertions(+), 2 deletions(-)
diff --git a/target-arm/cpu.h b/target-arm/cpu.h
index 24a910b..68ef363 100644
--- a/target-arm/cpu.h
+++ b/target-arm/cpu.h
@@ -355,6 +355,7 @@ typedef struct CPUARMState {
};
uint64_t c14_cntfrq; /* Counter Frequency register */
uint64_t c14_cntkctl; /* Timer Control register */
+ uint32_t cnthctl_el2; /* Counter/Timer Hyp Control register */
uint64_t cntvoff_el2; /* Counter Virtual Offset register */
ARMGenericTimer c14_timer[NUM_GTIMERS];
uint32_t c15_cpar; /* XScale Coprocessor Access Register */
diff --git a/target-arm/helper.c b/target-arm/helper.c
index f5579fc..299fbb9 100644
--- a/target-arm/helper.c
+++ b/target-arm/helper.c
@@ -1161,8 +1161,18 @@ static CPAccessResult gt_cntfrq_access(CPUARMState *env,
const ARMCPRegInfo *ri)
static CPAccessResult gt_counter_access(CPUARMState *env, int timeridx)
{
+ unsigned int cur_el = arm_current_el(env);
+ bool secure = arm_is_secure(env);
+
+ if (arm_feature(env, ARM_FEATURE_EL2) &&
+ timeridx == GTIMER_PHYS && !secure && cur_el < 2 &&
+ !extract32(env->cp15.cnthctl_el2, 0, 1)) {
+ env->exception.target_el = 2;
+ return CP_ACCESS_TRAP;
+ }
+
/* CNT[PV]CT: not visible from PL0 if ELO[PV]CTEN is zero */
- if (arm_current_el(env) == 0 &&
+ if (cur_el == 0 &&
!extract32(env->cp15.c14_cntkctl, timeridx, 1)) {
return CP_ACCESS_TRAP;
}
@@ -1171,10 +1181,21 @@ static CPAccessResult gt_counter_access(CPUARMState
*env, int timeridx)
static CPAccessResult gt_timer_access(CPUARMState *env, int timeridx)
{
+ unsigned int cur_el = arm_current_el(env);
+ bool secure = arm_is_secure(env);
+
+ if (arm_feature(env, ARM_FEATURE_EL2)) {
+ if (timeridx == GTIMER_PHYS && !secure && cur_el < 2 &&
+ !extract32(env->cp15.cnthctl_el2, 1, 1)) {
+ env->exception.target_el = 2;
+ return CP_ACCESS_TRAP;
+ }
+ }
+
/* CNT[PV]_CVAL, CNT[PV]_CTL, CNT[PV]_TVAL: not visible from PL0 if
* EL0[PV]TEN is zero.
*/
- if (arm_current_el(env) == 0 &&
+ if (cur_el == 0 &&
!extract32(env->cp15.c14_cntkctl, 9 - timeridx, 1)) {
return CP_ACCESS_TRAP;
}
@@ -2565,6 +2586,9 @@ static const ARMCPRegInfo v8_el3_no_el2_cp_reginfo[] = {
{ .name = "HTTBR", .cp = 15, .crm = 2, .opc1 = 4,
.access = PL2_RW, .type = ARM_CP_64BIT | ARM_CP_CONST,
.resetvalue = 0 },
+ { .name = "CNTHCTL_EL2", .state = ARM_CP_STATE_BOTH,
+ .opc0 = 3, .opc1 = 4, .crn = 14, .crm = 1, .opc2 = 0,
+ .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
{ .name = "CNTVOFF_EL2", .state = ARM_CP_STATE_AA64,
.opc0 = 3, .opc1 = 4, .crn = 14, .crm = 0, .opc2 = 3,
.access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
@@ -2684,6 +2708,10 @@ static const ARMCPRegInfo v8_el2_cp_reginfo[] = {
.type = ARM_CP_NO_RAW, .access = PL2_W,
.writefn = tlbi_aa64_vaa_write },
#ifndef CONFIG_USER_ONLY
+ { .name = "CNTHCTL_EL2", .state = ARM_CP_STATE_BOTH,
+ .opc0 = 3, .opc1 = 4, .crn = 14, .crm = 1, .opc2 = 0,
+ .access = PL2_RW, .resetvalue = 3,
+ .fieldoffset = offsetof(CPUARMState, cp15.cnthctl_el2) },
{ .name = "CNTVOFF_EL2", .state = ARM_CP_STATE_AA64,
.opc0 = 3, .opc1 = 4, .crn = 14, .crm = 0, .opc2 = 3,
.access = PL2_RW, .type = ARM_CP_IO, .resetvalue = 0,
--
1.9.1
- [Qemu-devel] [PATCH v2 01/14] target-arm: Break down TLB_LOCKDOWN, (continued)
- [Qemu-devel] [PATCH v2 01/14] target-arm: Break down TLB_LOCKDOWN, Edgar E. Iglesias, 2015/05/27
- [Qemu-devel] [PATCH v2 02/14] target-arm: Add MAIR_EL2, Edgar E. Iglesias, 2015/05/27
- [Qemu-devel] [PATCH v2 03/14] target-arm: Add TCR_EL2, Edgar E. Iglesias, 2015/05/27
- [Qemu-devel] [PATCH v2 04/14] target-arm: Add SCTLR_EL2, Edgar E. Iglesias, 2015/05/27
- [Qemu-devel] [PATCH v2 05/14] target-arm: Add TPIDR_EL2, Edgar E. Iglesias, 2015/05/27
- [Qemu-devel] [PATCH v2 06/14] target-arm: Add TTBR0_EL2, Edgar E. Iglesias, 2015/05/27
- [Qemu-devel] [PATCH v2 07/14] target-arm: Add TLBI_ALLE1{IS}, Edgar E. Iglesias, 2015/05/27
- [Qemu-devel] [PATCH v2 08/14] target-arm: Add TLBI_ALLE2, Edgar E. Iglesias, 2015/05/27
- [Qemu-devel] [PATCH v2 09/14] target-arm: Add TLBI_VAE2{IS}, Edgar E. Iglesias, 2015/05/27
- [Qemu-devel] [PATCH v2 10/14] target-arm: Add CNTVOFF_EL2, Edgar E. Iglesias, 2015/05/27
- [Qemu-devel] [PATCH v2 11/14] target-arm: Add CNTHCTL_EL2,
Edgar E. Iglesias <=
- [Qemu-devel] [PATCH v2 12/14] target-arm: Pass timeridx as argument to various timer functions, Edgar E. Iglesias, 2015/05/27
- [Qemu-devel] [PATCH v2 13/14] target-arm: Add HYP timer, Edgar E. Iglesias, 2015/05/27
- [Qemu-devel] [PATCH v2 14/14] hw/arm/virt: Connect the Hypervisor timer, Edgar E. Iglesias, 2015/05/27