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[Qemu-devel] [PULL 59/62] q35: implement TSEG
From: |
Paolo Bonzini |
Subject: |
[Qemu-devel] [PULL 59/62] q35: implement TSEG |
Date: |
Fri, 5 Jun 2015 17:16:00 +0200 |
From: Gerd Hoffmann <address@hidden>
TSEG provides larger amounts of SMRAM than the 128 KB available with
legacy SMRAM and high SMRAM.
Route access to tseg into nowhere when enabled, for both cpus and
busmaster dma, and add tseg window to smram region, so cpus can access
it in smm mode.
Signed-off-by: Gerd Hoffmann <address@hidden>
Acked-by: Michael S. Tsirkin <address@hidden>
Signed-off-by: Paolo Bonzini <address@hidden>
---
hw/pci-host/q35.c | 70 +++++++++++++++++++++++++++++++++++++++++++++++
include/hw/pci-host/q35.h | 1 +
2 files changed, 71 insertions(+)
diff --git a/hw/pci-host/q35.c b/hw/pci-host/q35.c
index 305994b..bd74094 100644
--- a/hw/pci-host/q35.c
+++ b/hw/pci-host/q35.c
@@ -198,6 +198,28 @@ static const TypeInfo q35_host_info = {
* MCH D0:F0
*/
+static uint64_t tseg_blackhole_read(void *ptr, hwaddr reg, unsigned size)
+{
+ return 0xffffffff;
+}
+
+static void tseg_blackhole_write(void *opaque, hwaddr addr, uint64_t val,
+ unsigned width)
+{
+ /* nothing */
+}
+
+static const MemoryRegionOps tseg_blackhole_ops = {
+ .read = tseg_blackhole_read,
+ .write = tseg_blackhole_write,
+ .endianness = DEVICE_NATIVE_ENDIAN,
+ .valid.min_access_size = 1,
+ .valid.max_access_size = 4,
+ .impl.min_access_size = 4,
+ .impl.max_access_size = 4,
+ .endianness = DEVICE_LITTLE_ENDIAN,
+};
+
/* PCIe MMCFG */
static void mch_update_pciexbar(MCHPCIState *mch)
{
@@ -267,6 +289,7 @@ static void mch_update_smram(MCHPCIState *mch)
{
PCIDevice *pd = PCI_DEVICE(mch);
bool h_smrame = (pd->config[MCH_HOST_BRIDGE_ESMRAMC] &
MCH_HOST_BRIDGE_ESMRAMC_H_SMRAME);
+ uint32_t tseg_size;
/* implement SMRAM.D_LCK */
if (pd->config[MCH_HOST_BRIDGE_SMRAM] & MCH_HOST_BRIDGE_SMRAM_D_LCK) {
@@ -296,6 +319,39 @@ static void mch_update_smram(MCHPCIState *mch)
memory_region_set_enabled(&mch->high_smram, false);
}
+ if (pd->config[MCH_HOST_BRIDGE_ESMRAMC] & MCH_HOST_BRIDGE_ESMRAMC_T_EN) {
+ switch (pd->config[MCH_HOST_BRIDGE_ESMRAMC] &
+ MCH_HOST_BRIDGE_ESMRAMC_TSEG_SZ_MASK) {
+ case MCH_HOST_BRIDGE_ESMRAMC_TSEG_SZ_1MB:
+ tseg_size = 1024 * 1024;
+ break;
+ case MCH_HOST_BRIDGE_ESMRAMC_TSEG_SZ_2MB:
+ tseg_size = 1024 * 1024 * 2;
+ break;
+ case MCH_HOST_BRIDGE_ESMRAMC_TSEG_SZ_8MB:
+ tseg_size = 1024 * 1024 * 8;
+ break;
+ default:
+ tseg_size = 0;
+ break;
+ }
+ } else {
+ tseg_size = 0;
+ }
+ memory_region_del_subregion(mch->system_memory, &mch->tseg_blackhole);
+ memory_region_set_enabled(&mch->tseg_blackhole, tseg_size);
+ memory_region_set_size(&mch->tseg_blackhole, tseg_size);
+ memory_region_add_subregion_overlap(mch->system_memory,
+ mch->below_4g_mem_size - tseg_size,
+ &mch->tseg_blackhole, 1);
+
+ memory_region_set_enabled(&mch->tseg_window, tseg_size);
+ memory_region_set_size(&mch->tseg_window, tseg_size);
+ memory_region_set_address(&mch->tseg_window,
+ mch->below_4g_mem_size - tseg_size);
+ memory_region_set_alias_offset(&mch->tseg_window,
+ mch->below_4g_mem_size - tseg_size);
+
memory_region_transaction_commit();
}
@@ -443,6 +499,20 @@ static void mch_realize(PCIDevice *d, Error **errp)
mch->ram_memory, 0xa0000, 0x20000);
memory_region_set_enabled(&mch->high_smram, true);
memory_region_add_subregion(&mch->smram, 0xfeda0000, &mch->high_smram);
+
+ memory_region_init_io(&mch->tseg_blackhole, OBJECT(mch),
+ &tseg_blackhole_ops, NULL,
+ "tseg-blackhole", 0);
+ memory_region_set_enabled(&mch->tseg_blackhole, false);
+ memory_region_add_subregion_overlap(mch->system_memory,
+ mch->below_4g_mem_size,
+ &mch->tseg_blackhole, 1);
+
+ memory_region_init_alias(&mch->tseg_window, OBJECT(mch), "tseg-window",
+ mch->ram_memory, mch->below_4g_mem_size, 0);
+ memory_region_set_enabled(&mch->tseg_window, false);
+ memory_region_add_subregion(&mch->smram, mch->below_4g_mem_size,
+ &mch->tseg_window);
object_property_add_const_link(qdev_get_machine(), "smram",
OBJECT(&mch->smram), &error_abort);
diff --git a/include/hw/pci-host/q35.h b/include/hw/pci-host/q35.h
index 113cbe8..dbe6dc0 100644
--- a/include/hw/pci-host/q35.h
+++ b/include/hw/pci-host/q35.h
@@ -54,6 +54,7 @@ typedef struct MCHPCIState {
PAMMemoryRegion pam_regions[13];
MemoryRegion smram_region, open_high_smram;
MemoryRegion smram, low_smram, high_smram;
+ MemoryRegion tseg_blackhole, tseg_window;
PcPciInfo pci_info;
ram_addr_t below_4g_mem_size;
ram_addr_t above_4g_mem_size;
--
2.4.1
- [Qemu-devel] [PULL 50/62] target-i386: create a separate AddressSpace for each CPU, (continued)
- [Qemu-devel] [PULL 50/62] target-i386: create a separate AddressSpace for each CPU, Paolo Bonzini, 2015/06/05
- [Qemu-devel] [PULL 51/62] hw/i386: add a separate region that tracks the SMRAME bit, Paolo Bonzini, 2015/06/05
- [Qemu-devel] [PULL 53/62] hw/i386: remove smram_update, Paolo Bonzini, 2015/06/05
- [Qemu-devel] [PULL 52/62] target-i386: use memory API to implement SMRAM, Paolo Bonzini, 2015/06/05
- [Qemu-devel] [PULL 54/62] q35: implement high SMRAM, Paolo Bonzini, 2015/06/05
- [Qemu-devel] [PULL 55/62] q35: fix ESMRAMC default, Paolo Bonzini, 2015/06/05
- [Qemu-devel] [PULL 56/62] q35: add config space wmask for SMRAM and ESMRAMC, Paolo Bonzini, 2015/06/05
- [Qemu-devel] [PULL 57/62] q35: implement SMRAM.D_LCK, Paolo Bonzini, 2015/06/05
- [Qemu-devel] [PULL 58/62] q35: add test for SMRAM.D_LCK, Paolo Bonzini, 2015/06/05
- [Qemu-devel] [PULL 60/62] ich9: implement SMI_LOCK, Paolo Bonzini, 2015/06/05
- [Qemu-devel] [PULL 59/62] q35: implement TSEG,
Paolo Bonzini <=
- [Qemu-devel] [PULL 61/62] atomics: add explicit compiler fence in __atomic memory barriers, Paolo Bonzini, 2015/06/05
- [Qemu-devel] [PULL 62/62] update Linux headers from kvm/next, Paolo Bonzini, 2015/06/05
- Re: [Qemu-devel] [PULL 00/62] KVM, dirty bitmap, build system, SMM, icount changes for 2015-06-05, Paolo Bonzini, 2015/06/05